Abstract: The present invention is directed to a method and system for the efficient transmission of electromagnetic radiation through a channel. An electromagnetic radiation guide of the present invention may include an optical channel having a refractive and transmissive index capable of guiding electromagnetic radiation through the guide. The electromagnetic radiation guide may also include an optical prismatic section capable of redirecting electromagnetic waves to allow increased light transmission by reducing losses from refracted light rays.
Abstract: An apparatus comprising one or more enclosures and a controller. The one or more enclosures may each comprise one or more drives. The controller may be configured to map correctly correlating addresses to one or more drives. An advantageous aspect of the present invention is the ability to support general enclosure wiring when associating data with physical devices, such as associating SES data with physical devices on a fiber channel loop with soft addresses.
Abstract: The present invention is directed to a uniform airflow diffuser for utilization in a process chamber, such as a process chamber utilized in the manufacture of semiconductor chips. The uniform airflow diffuser is suitable for generating a back flow of air sufficient to cause the airflow to be distributed across the airflow diffuser. The resultant build-up in pressure in the plenum area may result in uniform airflow through a plurality of holes included in the airflow diffuser yielding substantially laminar airflow through the chamber.
Abstract: In a computerized data storage system, when data is to be updated in a primary, or “base,” logical volume, a snapshot volume is formed from the base volume. The updates are then made to the snapshot volume, preferably while the base volume is still used to satisfy normal I/O (input/output) access requests. After the updating is complete, the snapshot volume is rolled back into the base volume. During the rollback, any remaining original data in the base volume and the updated data in either the base volume or snapshot volume are available for satisfying the normal I/O access requests. Thus, the updating appears to be instantaneous, since the entire updated data is immediately available upon starting the rollback.
Abstract: The present invention is directed to a system and method for tuning retry performance of read requests of data from electronic data storage devices. In an aspect of the present invention, a method for performing a delayed read in an electronic data storage system having an initiator and a target device may include initiating a delayed read by the initiator to the target device and issuing at least one delayed read. The initiator then delays for a programmed interval before reissuing the at least one delayed read.
Abstract: Stable cellulosic fiber material for use in forming zeolite/cellulose composites is prepared by suspending loose cellulose fibers in an aqueous solution of sodium hydroxide, potassium hydroxide or sodium silicate, stirring the resulting suspension until it reaches a macroscopically homogenous appearance, heating the resulting mixture at a temperature of 323-423 K until only dry solids remain, contacting the resulting mixture with excess distilled water to remove physically adsorbed or trapped sodium hydroxide, potassium hydroxide or sodium silicate from the fibers, and heating the resulting fiber material at 323-423 K to dry the fiber material. Stable zeolite/cellulose composite material characterized in that leaching of the zeolite phase does not occur upon contact of the composite with water at approximately 373 K comprises a zeolite and a stable cellulosic fiber prepared as described above, the composite material being formed by contacting a zeolite with the stable fiber material.
Type:
Grant
Filed:
August 6, 2002
Date of Patent:
November 9, 2004
Assignees:
Board of Regents of the University of Nebraska, Kraft Foods Inc.
Inventors:
Gustavo Larsen, David Vu, Manuel Marquez-Sanchez
Abstract: The present invention is directed to a host interface bypass on a fabric based array controller. An apparatus of the present invention may include an external electronic device suitable for performing a function, a controller and a fabric connection. The controller includes at least one internal module, the internal module providing a controller function. The fabric connection communicatively connects the external device to the controller, wherein the module of the controller is directly accessible by the external electronic device.
Abstract: The present invention is directed to an optical proximity correction driven hierarchy. A method for constructing a hierarchy of optically independent structures for use in optical proximity correction of a circuit may include receiving an integrated circuit design, the design including geometric circuit elements for providing circuit functions of an integrated circuit. At least a portion of the integrated circuit design is exploded and geometric circuit elements of the exploded integrated circuit design are gathered into optically independent classes. A search is then performed for congruency for each optically independent class.
Type:
Grant
Filed:
March 14, 2002
Date of Patent:
November 2, 2004
Assignee:
LSI Logic Corporation
Inventors:
Stanislav V. Aleshin, Evgueny E. Egorov, Marina Medvedeva
Abstract: The present invention is directed to a system and method of providing an integrated dynamic multipathing filter. A method of providing a data transfer between a host and a target in a network environment may include providing a logical identifier table by an input/output interface. The logical identifier table includes at least one logical identifier suitable for referencing a physical address identifier of a target. Communications between the host and the target are managed by selecting a route by the input/output interface from at least two routes associated with a logical identifier, the at least two routes communicatively coupling the input/output interface to the target so that the host may access the target utilizing the logical identifier.
Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.
Abstract: A blind setting rivet assembly capable of permanently fastening one or more sheet metal work pieces or the like together is disclosed. The rivet assembly may be self polishing and self tapping and may also provide a hollow cylindrical threaded bolt head onto which a nut may be affixed to provide a means to removably attach other work pieces, components or the like. The rivet assembly comprises a rivet body having a hollow tubular sleeve and an enlarged flattened head. The rivet body surrounds a mandrel that may have a weakened area of reduced diameter to allow detachment of the mandrel shaft following application of sufficient axial force to the shank. This application of force sets the rivet by causing a tapered shoulder section of the mandrel to deform the rivet sleeve. The mandrel shank may be terminated in a screw tip. This screw tip punctures, spreads, self-taps, and self-polishes an aperture in the work pieces through which the rivet sleeve passes.
Abstract: An architecture is described having characteristics, scale and realized according to a minimized cost function with the ability to control and govern liability, availability, band width, capacity and quality of service as one pleases subject to a desired type of management software or framework.
Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.