Abstract: Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking circuitry are all as wide as one side of the RAM array, and are all communicable with each other via data transfer means. This allows wide word processing, user configurable for parallel processing. Bits masked by the masking circuitry are selectable by data in the bidirectional shift register, providing shiftable masking means. Random access and serial access are done through separate ports. The bidirectional shift register is optionally serially accessible. Methods of use are also presented.

Abstract: The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operation, thus test time can be decreased.

Abstract: The invention is a process for cleaning a chamber after a chemical vapor deposition has been performed therein. A residue formed during the deposition is combined with a reactive species to form a gas containing an organic substance once found in the residue and to form a film on the chamber walls and internal parts. The gas and the film are removed from the chamber. The formation of a polymer byproduct on the chamber walls and other internal parts of the chamber is minimized by the method of the invention.

Abstract: A method and circuit for generating a self-refresh mode signal and a self-refresh cycle signal. The circuit is a dynamic random access memory (DRAM) device having a control array of control cells charged to a potential by a current source and having a monitor circuit for monitoring the potential of the control array. The DRAM comprises a discharge circuit which discharges the potential of the control array in response to the monitor circuit detecting when the potential of the control array has reached a trip point. A counter circuit counts the number of cycles of charge and discharge and generates the self-refresh mode signal after a desired count is reached. The counter circuit continues to count the number of cycles of charge and discharge while in the refresh mode and generates a self-refresh cycle signal each time the counter circuit counts a desired number of counts.

Abstract: The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

Abstract: The invention is a circuit and method for maintaining a negative potential, with respect to the digit line potential, on non-selected wordlines.

Abstract: A circuit and method for preventing glitches from occurring during a termination of a self-refresh mode when a race condition exits between an external row address strobe signal* (RAS*) transitioning to an inactive state and an internally generated self-refresh timing signal transitioning to an inactive state. The circuit of the invention includes a pulse circuit for generating an active self-refresh cycle pulse and a lock out circuit. The lock out circuit is responsive to the external RAS* signal and the active self-refresh cycle pulse. The lock out circuit locks out the effect of the active self-refresh cycle pulse when an external RAS* signal transitions to an inactive state prior to the generation of the active self-refresh cycle pulse and locks out an effect of a transition of the external RAS* signal to an inactive state when the active self-refresh cycle pulse is present.

Abstract: A semiconductor circuit module is formed with external connections on coaxial pins. This provides a controlled impedance between a ground connection and a signal connection which is substantially equal per unit length. The module may be configured so that the impedance of the connection between the signal connections and integrated circuit may also be optimally impedance matched.

Abstract: There is a precharge circuitry that uses little real estate and can be deactivated once a word line driver is activated. Specifically, a high signal created by the selected driver is fed back to the precharge circuit to deactivate it when activating a chosen word line. Thus, alleviating the resulting effect between the low signal to activate the selected driver and the precharge high voltage current both using the same node coupled to the word line drivers.

Abstract: A video RAM having isolated array sections for providing write function that will not affect other array sections. The whole VRAM memory array does not have to be completely read before writing new pixel information to particular array section. At least two separate VRAM activities can be performed simultaneously to different parts of the array. Specifically, to write to one particular section of an array and to and for refreshing other parts of the VRAM. The overall read and write sequences can be shorter. When a particular pixel or memory cell has to be modified or update, only an associated SAM to the particular cell will be activated. This SAM will now only affect the column lines associated with that section of the array containing the activated SAM.

Abstract: The invention is a method directed to the use of a nonvolatile precursor, either a solid precursor or a liquid precursor, suitable for chemical vapor deposition (CVD), including liquid source CVD (LSCVD), of a semiconductor film. Using the method of the invention the nonvolatile precursor is dissolved in a solvent. The choice of solvent is typically an inorganic compound that has a moderate to high vapor pressure at room temperature and that can be liquified by a combination of pressure and cooling. The solution thus formed is then transported at an elevated pressure and/or a reduced temperature to the CVD chamber. In CVD the solution evaporates at a higher temperature and a lower pressure upon entry to the CVD chamber, and the nonvolatile precursor, in its gaseous state, along with a gas reactant, produces a product which is deposited as a thin film on a semiconductor wafer.

Abstract: A charge pump circuit and method for increasing a value of a supply potential. The charge pump circuit features a first stage circuit for generating an intermediate pumped potential greater than an input supply potential. The intermediate pumped potential becomes a supply potential for a portion of a second stage circuit. The second stage circuit generates a pumped output potential greater than the intermediate pumped potential. Both the first and second stage circuits have at least two capacitors, a small pump capacitor and a large pump capacitor. The first stage circuit of the invention supplies the increased intermediate pumped potential to those nodes which are used to charge the small pump capacitor of the second stage circuit. The input supply potential supplies the potential to those nodes which are used to charge the large pump capacitors of both stages and the small pump capacitor of the first stage circuit.

Abstract: The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is then formed in the recess. The process is continued with a formation of a second insulative layer, a potion of which is removed to form an opening exposing a portion of the barrier layer. An oxidation resistant conductive layer is deposited in the recess and forms at least a portion the storage node electrode of the capacitor.

Abstract: An integral process is provided for depositing onto, and etching a layer of copper from, a multi-layer structure. The subject process, which is conducted within a vacuum chamber, comprises providing a multi-layer having at least one major surface in which contact/vias are located. Next, a copper precursor is deposited onto at least one major surface of the multi-layer structure and into the contact/vias. The substrate temperature of the multi-layer structure in the vacuum chamber is maintained above the decomposition temperature of the copper precursor during the deposition thereof. In the etching phase of the integral process, an protective etch mask is provided on the major surface. Then, the substrate temperature of the multi-layer structure is lowered in the vacuum chamber below the decomposition temperature of the deposited copper precursor. Etching of the deposited copper film is then conducted employing an etchant material comprising the decomposition product of the copper precursor.

Abstract: There is a post etching test apparatus and method to be able to only test just a few die on the wafer. Uniquely, the remainder of the die on the wafer can be salvaged, if the test identifies proper tolerances for the etching process over the entire wafer surface. If the tests show negative, the etch process can be re calibrated and the wafer can be reprocessed and tested again. Salvage of the majority of the die on the wafer under test is possible by using a fine point resist removal plate. Specifically, oxygen is forced over certain die on the wafer to remove the resist mask by using a plate barrier with only a few holes in it. The holes are located a key positions around the wafer, and restrain the oxygen laminar flow to effect only the wafers directly below these holes.

Abstract: The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. Titanium is deposited and a rapid thermal anneal is performed. The titanium reacts with silicide of the conductive plug to form TiSi at the bottom of the recess. Unreacted Ti is removed. The barrier layer is then formed in the recess.

Abstract: The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

Abstract: The invention is a circuit and method for controlling a high potential at a significant node by controlling the potential at a control input to an electrical device in electrical communication with the significant node. The potential of the control input is controlled by a control circuit. In a first embodiment the control circuit is a potential generator, and in a second embodiment the control circuit is a programmable circuit. The programmable circuit provides a potential at the control input that is directly proportional to a supply potential until a maximum potential is reached at which time the control input is maintained at the maximum potential.

Abstract: An output driver circuit of a DRAM is wired in a push-pull arrangement. A CMOS transistor arrangement provides a strong output signal. This transistor arrangement comprises the pull-up transistor circuit of the push-pull arrangement. A bootstrap circuit gates the NMOS of the CMOS causing an incremental increase in CMOS drain current. The invention is an enhancement circuit for ensuring the deactuation of the pull-down portion of the push-pull arrangement during the action of the CMOS transistor arrangement.

Abstract: The invention is a method for synchronizing the refresh cycles of a bank of self-refreshing interruptable DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing interruptable DRAM to its respective external refresh pin.