Abstract: Deformation of a lifting ring of bimetallic structure or memory metal is matched to a solder softening or melting temperature to apply forces to lift a chip from a supporting structure, such as a substrate or multi-chip module, only when the solder connections between the chip and the supporting structure are softened or melted. The temperature of the chip, module and solder connections there between is achieved in a commercially available box oven or belt furnace or the like and results in much reduced internal chip temperatures and thermal gradients within the chip as compared to known hot chip removal processes. Tensile and/or shear forces at solder connections and chip and substrate contacts are much reduced in comparison with known cold chip removal processes. Accordingly, the process is repeatable at will without significant damage to or alteration of electrical characteristics of the chip or substrate.

Abstract: A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull-up devices is minimized.

Abstract: A reduced power programmable logic array is disclosed. The circuit includes an AND array, coupled through product term lines to an output OR array. Pull-up devices in the OR array are gated to one of the active product term lines. Also disclosed is method for choosing a product term line for gating pull-up devices such that power consumption in the pull-up devices is minimized.