Abstract: A modeling module is disclosed that couples to a modular platform chassis. The modeling module includes a resident management controller to implement a test to model a component layout for a module to be received and coupled to the modular platform chassis. The test includes an operating thermal load for a component resident on the module at a given location. The module has a dimensional length and width that is similar to that of the modeling module. The modeling module also includes a thermal load device that is responsive to the management controller. The thermal load device is to implement at least a portion of the test by simulating the operating thermal load for the component resident on the module at the given location.

Abstract: For a battery-operable device, an overload protector may prevent a catastrophic malfunction. Using the overload protector, a power source may enable controlled delivery of power to the battery-operable device as a result of a timely intervention. More particularly, in mobile devices or systems with variable power consumption components and/or operational modes, the frequency of the occurrence of tripping in a battery may be reduced or even eliminated in some cases. In one embodiment, a battery overload protector may continuously monitor available power from a power delivery unit and alert a processor-based system before a threshold of available power is reached by tracking power consumption against the threshold. The battery overload protector may issue a warning to the processor-based system in order to avoid exceeding the threshold.

Abstract: A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.

Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet for a request transaction to a receiving device. The receiving device checks for error conditions. If an error condition exists and if the packet for the request transaction indicates that a completion is not expected by the transmitting device, an error message is delivered by the receiving device to the transmitting device.

Abstract: A requesting device and a completer device are coupled via a high-speed serial interface within a computer system. The requesting device transmits a packet for a request transaction to a completer device. The completer device checks for error conditions in the course of servicing the request. If an error condition is found then the completer device transmits a completion packet with a completion status of something other than successful. The completion packet includes a completer identification field. The requesting device records the completer identification value and indicates in a register that a completion packet has been received with a non-successful completion status.

Abstract: A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.

Abstract: A method and apparatus for balancing memory access latency and bandwidth is generally described. In accordance with one example embodiment of the invention, a method comprising determining at least one characteristic of a memory request, and selectively leaving an accessed memory page open after a memory access based, at least in part, on the at least one characteristic for the memory request, to balance memory access latency and bandwidth of a subsequent memory request(s).

Abstract: A virtual machine receives a first set of code. At least a portion of the first set of code is provided to a compiler and is partitioned into a plurality of groupings of code. At least one of the groupings of code is compiled into a plurality of second sets of code. At least two of the second sets of code are provided to differing processor resources. The differing processor resources include a plurality of processing elements embodied on one processor device.

Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type.

Abstract: A gold code generator is described comprising two pairs of linear feedback shift registers, the seed values for the second pair of linear feedback shift registers are different from the seed values for the first pair of linear feedback shift registers. The second seed values are calculated from the first seed values. The use of this second pair of linear feedback shift registers prevents the need to use a wide span of taps to the linear feedback shift register to produce output bits. By using two pairs of linear feedback shift registers, a parallel output implementation can be produced in which multiple output bits are produced in a single clock cycle.

Abstract: A switching fabric for transmitting digital data from a plurality of sources to a plurality of destinations is described. The switching fabric includes a plurality of input ports, a plurality of output ports and a plurality of switching sections. Each of the input ports receives data frames and partitions the received data payload of at least some of the frames into a plurality of associated data cells. Each of the output ports are coupled to at least one destination associated with the headers of the data frames. Each of the switching sections may be coupled to each of the input ports and each of the output ports for transmitting each of selected ones of the data cells from the at least one input port to one or more of the coupled output ports.

Abstract: A network switch having a plurality of port blades, each port blade having a media port and an input and an output connection. The network switch includes a slot adapted to receive a first switch fabric blade in one of a plurality of positions. The first switch fabric blade is configured to receive a subset of the input connections and output connections from the port blades. Multiple switch fabric blades can be inserted into the slot to receive a different subset of the connections. In this manner, a low-cost modular network switch can be designed that can easily be scaled as bandwidth requirements increase.

Abstract: A modular server system includes a midplane having a system management bus and a plurality of blade interfaces on the midplane. The blade interfaces are in electrical communication with each other. A server blade is removeably connectable to one of the plurality of blade interfaces on the midplane. The server blade has a server blade system management bus in electrical communication with the system management bus of the midplane, and a network interface to connect to a network. A media blade is removeably connectable to one of the plurality of blade interfaces on the midplane, and the media blade has at least one storage medium device.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of using a bypass buffer in a node coupled to a ringlet includes the steps of: writing a packet of binary digital signals on the ringlet into the bypass buffer; and retaining the packet of binary digital signals in the bypass buffer for a predetermined amount of time before transferring the packet to the ringlet. Briefly, in accordance with another embodiment, a node to be coupled to a ringlet includes: a transmit buffer and a receive buffer. The transmit and receive buffers are coupled in a configuration to transfer binary digital signals between the node and the ringlet via the transmit and receive buffers. The configuration further includes a bypass buffer to temporarily queue binary digital signals passing through the node. The bypass buffer is further coupled in the configuration to retain a packet of binary digital signals for a predetermined amount of time before transferring the packet to the ringlet.