Abstract: A Fetch-Then-Confirm (FTC) policy is used for the handling of data fetch upon XIEX's in a tightly coupled multiprocessor environment. The fetch and/or use of a requested data line upon XIEX is allowed before the SCE receives the confirmation of validity (or invalidity) of the requested line through the clearing procedure. Whenever a line having uncertain validity is used by a CP the results of execution of instructions depending on the validity of the line should not be committed to the cache until a confirmation is received from the SCE. When the confirmation from the SCE indicates that a line L is known to be valid, all results depending on the validity of L can be processed as usual. If, however, the SCE indicates that a previously fetched line L having uncertain validity is in fact invalid, all operations performed based on L's contents should be aborted and restarted properly when a valid copy of L is received.

Abstract: A method for storing into a non-EX cache line in a multiprocessor system. Upon a store into a non-EX line the instruction execution and the processing of subsequent instructions will continue. The results of the current instruction, however, and any subsequent instruction whose decode and execution depends upon the result of the current instruction or that requires operand fetches, will not be released until the processing of the current instruction is resolved. The request to store into the non-EX line is simultaneously sent to the SCE to obtain the EX state for the line. The SCE serializes storage requests. When a request for EX state is processed, certain XI actions (e.g. XI-invalidates) may be invoked. Any instruction using fetched data XI-invalidated before the resolution of a preceding store at the same CP is considered likely to be invalid, and redone.

Abstract: A modular fail-safe memory and an address generation mechanism that provides load balancing when the memory is shared by a number of processors. A plurality of memory modules are used for the memory with no specific limit on the number of memory modules, and a checksum block is used to back-up corresponding blocks in the other memory modules. The checksum blocks are distributed across the memory modules, and an address generation mechanism determines the checksum location for a specific memory block. This address generation mechanism ensures that checksum blocks are equally divided between the memory modules so that there is no memory bottleneck, is easy to implement in hardware, and is extended to provide similar properties when a module failure occurs.

Abstract: A single floating point that produces the result A.times.B+C with A, B and C being floating point numbers. The operand C is shifted in parallel with the beginning phases of the multiplication. The result is produced after a single addition and normalization, reducing hardware, delay and rounding errors.

Abstract: Apparatus for fetching instructions in a computing system. A broadband branch history table is organized by cache line. The broadband branch history table determines from the history of branches the next cache line to be referenced and uses that information for prefetching lines into the cache.

Abstract: A method for selecting a limited number of presentation colors from a larger palette for a selected image. A three dimensional color histogram of said image is generated and a first color is selected based upon the color occurring most frequently in the image. Subsequent presentation colors are selected by choosing one at a time those colors having the highest weighted frequency of occurrence wherein the weighting is such that colors closest to the previously selected color are weighted very little while colors furthest away from the previously selected color are weighted the most.

Abstract: A method for carrying out morphic transformations with minimal memory accesses by using a two step convolving sequence to form an intermediate image. The components of the intermediate image are used in a recursive process to provide the desired final convolution. The word resulting from this convolution is then used to access a morphic transformation table in a second memory access for table hookup. The two step convolution requires a total of only two memory reads and two memory writes.

Abstract: Apparatus and method for processing multi-valved images includes an erosion filter and a dilation filter. The erosion filter determines the frequency with which a pixel having the same value as a pixel at a first check position of a first window appears in the first window. If the frequency of appearance is equal to or less than a value predetermined for the pixel value of the first check position, the pixel value at the first check position is made null. This operation is recursively executed while scanning a multi-valved image with the first window. The dilation filter replaces any null pixel value at a second check position of a second window with a selected non-null pixel value in the second window. The selected non-null value has the maximum frequency of appearance in the second window. This operation is also recursively executed while scanning the multi-valved image with the second window.

Abstract: A memory system backup for use in a tightly or loosely coupled multiprocessor system. A plurality of primary memory units having substantially the same configuration are backed up by a single memory unit of similiar configuration. The backup memory unit holds the checksum of all data held in all primary memory units. In the event of the failure of one of the primary memory units its contents can be recreated based on the data in the remaining non-failed memory unit and the checksum in the backup unit.

Abstract: A high speed buffer store arrangement for use in a data processing system having multiple cache buffer storage units in a hierarchial arrangement permits fast transfer of wide data blocks. On each cache chip, input and output latches are integrated thus avoiding separate intermediate buffering. Input and output latches are interconnected by 64-byte wide data buses so that data blocks can be shifted rapidly from one cache hierarchy level to another and back. Chip-internal feedback connections from output to input latches allow data blocks to be selectively reentered into a cache after reading. An additional register array is provided so that data blocks can be furnished again after transfer from cache to main memory or CPU without accessing the respective cache. Wide data blocks can be transferred within one cycle, thus tying up caches much less in transfer operations, so that they have increased availability.

Abstract: A method and apparatus used to detect errors in a signal transmitted over a single wire. All transient errors are detected when the effect of the transient lasts for at least one cycle and not more than five cycles. Transient errors of longer duration will be detected if the level of the original signal at the start of the transient is different from that at the end of the transient. Stuck faults will be deleted if one onset of the stuck fault causes the level of the signal to change. Redundancy is incorporated by introducing redundant transitions in the signal on the same wire. This requires the successive transitions in the original signal to be at least three cycles apart. If a transition is viewed as a binary one and the absence of a transition as a binary zero then each binary one is replaced with the sequence "one-one-one" (overwriting subsequent zeros), and keeping each zero as the single bit "zero". Upon decoding, each group of three transitions is converted to a single transition.

Abstract: An image processing method and system wherein the virtual storage concept is introduced into the storage and management of image data so as to be adapted to an image processing. Data representing an image is stored on a block basis as data blocks corresponding to image strips in a virtual image, in a first storage device, having a plurality of storage blocks, corresponding to a virtual storage, and the data blocks to be processed are fetched from the first storage device into a second working storage device, having a smaller number of storage blocks than the plurality of storage blocks in the first storage device, corresponding to real storage, to perform image processing.

Abstract: A prefetching mechanism for a system having a cache has, in addition to the normal cache directory, a two-level shadow directory. When an information block is accessed, a parent identifier derived from the block address is stored in a first level of the shadow directory. The address of a subsequently accessed block is stored in the second level of the shadow directory, in a position associated with the first-level position of the respective parent identifier.With each access to an information block, a check is made whether the respective parent identifier is already stored in the first level of the shadow directory. If it is found, then a descendant address from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids, with a high probability, the occurrence of cache misses.

Abstract: A method and apparatus is provided for associating in cache directories the Control Domain Identifications (CDIDs) of software covered by each cache line. Through the use of such provision and/or the addition of Identifications of users actively using lines, cache coherence of certain data is controlled without performing conventional Cross-Interrogates (XIs), if the accesses to such objects are properly synchronized with locking type concurrency controls. Software protocols to caches are provided for the resource kernel to control the flushing of released cache lines. The parameters of these protocols are high level Domain Identifications and Task Identifications.

Abstract: A data processing system includes multiple floating point arithmetic units, for example, an adder and a multiplier. Two putaway busses and two bypass busses are connected to a register file and waiting stages, associated with the arithmetic units, respectively. A special source register is included for keeping track of the source of any result on the busses so that the registers may be connected to the appropriate bus on which the result is to appear in accordance with a busy or mark bit set in each register in the file and in the waiting stage. This allows multiple data items to exit the pipes during any cycle. Therefore, two or more results are produced each cycle.

Abstract: A data-dependent branch table is a mechanism that is sensitive to operands that will be tested in order to determine branch action outcomes. The data dependent branch table operates in conjunction with a branch history table to anticipate those instances where the branch history table will make an erroneous prediction, and corrects the branch history table prior to the time that the actual prediction is made.

Abstract: A method of generating the layout of CMOS cells from a high-level functional description of the cells, as well as generating the particular details of the CMOS device. In particular, the image of the chip is formed having the polysilicon gates of the transistors on the n-side vertically aligned with those of the p-side vertically aligned with those of the p-side to minimize the wiring effort. The interconnections between the source and drains are orthogonal to the gates, and run along one layer of metal.

Abstract: A shift register latch (SRL) arrangement for testing a combinational logic circuit, producing true and complement outputs in nature, has two clocked DC latches and additional circuitry for providing an input to the second latch. Clock signal trains and an extra TEST signal are used to control the SRL arrangement in different modes. In a first mode, one of the outputs from the combinational logic circuit is latched into the first latch and provided to a succeeding combinational logic circuit. In a second mode, a plurality of the SRL arrangements are interconnected together to form a shift register chain so that each latch acts as one position of the shift register chain. Further, in a third mode, the true and complement outputs of the combinational logic circuit are exclusive ORed and its result is latched into the second latch. During the third mode, output of the first latch is prevented from being latched into the second latch.

Abstract: A method for rotation of a binary image by 180 degrees, includes the steps of: positioning first and second address pointers at the center of at the beginning and end respectively of an image to be rotated; indexing the first pointer in a first direction through said image; indexing the second pointer in a second direction through said image; exchanging, for each index step, a first image word at the first pointer with a second image word, at the second pointer if the first image word and the second image word have any two bits with different values; reversing all exchanged words; storing the reversed, exchanged words at said pointer locations; repeating the above steps until the first pointer and the second pointer have been indexed through all words in the image at which point the image has been rotated by 180 degrees.

Abstract: A branch history table (BHT) is substantially improved by dividing it into two parts: an active area, and a backup area. The active area contains entries for a small number of branches which the processor can encounter in the near future and the backup area contains all other branch entries. Means are provided to bring entries from the backup area into the active area ahead of when the processor will use those entries. When entries are no longer needed they are removed from the active area and put into the backup area if not already there. New entries for the near future are brought in, so that the active area, though small, will almost always contain the branch information needed by the processor.The small size of the active area allows it to be fast and to be optimally located in the processor layout. The backup area can be located outside the critical part of the layout and can therefore be made larger than would be practicable for a standard BHT.