Abstract: Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

Abstract: The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

Abstract: Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.