Abstract: A structure which stores charge useful in a DRAM provides small cell size and eliminates subthreshold leakage current of the access transistor in the cell. Hence this is highly suitable for use for instance in ASICs (applications specific integrated circuits) which are fabricated using "logic" circuit fabrication techniques which normally do not accommodate DRAM cells. The DRAM charge storage structure includes a p-channel access transistor and an n-doped well in a p-doped substrate, a p-channel charge storage capacitor with its source/drain directly connected to the source region of the access field effect transistor, a source of a voltage to the gate of the storage capacitor, and a voltage source connected to the wordline and thereby to the gate terminal of the access transistor which switches between two voltage levels.

Abstract: A method of implementing a scan flipp for use with logic gates includes configuring the flip-flop into a scan mode or data mode. Then the flip-flop enters the precharge phase in which a dynamic input stage is precharged and a static output stage maintains the output signal from the previous evaluation phase. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

Abstract: A dual package container formed from a single-piece blank that is separable, for example, from a standard twelve-bottle container into first and second six-bottle packages. The first package includes an inner wall that is connected across a first fold line located along its lower edge to the inner wall of the second package. Tabs extending from top and bottom flaps of the first package are glued to corresponding top and bottom flaps of the second package. The tabs are attached the top and bottom flaps of the first package across second fold lines. The first and second fold lines are perforated to facilitate tearing during a separation process in which the first package is separated from the second package. The single-piece blank includes panels that form the walls of the first and second packages. Flanges extending from inner wall panels are respectively glued to end wall panels of the first and second packages.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array that requires periodic refresh operations. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. The apparatus includes a multi-bank DRAM memory and an SRAM cache that stores the most recently accessed data. Each of the DRAM banks is operated with independent control, thereby enabling parallel refresh operations and read-write accesses to different banks. The capacity of the SRAM cache is selected such that refresh operations can be carried out even under the condition of indefinite 100% access of the multi-bank DRAM memory.

Abstract: A restraint system which can remain on an animal at all times. In one embodiment, the restraint system includes a strap which serves as both a collar and a leash. The restraint system can be in either an extended state or a retracted state. In the extended state, the collar portion is positioned around the animal's neck and the leash portion extends from the collar portion to the animal owner's hand. In the retracted state, the entire restraint system is stored around the animal's neck by reversibly attaching the leash portion to the collar portion, as well as to the leash portion itself, in an overlapping spiral configuration. VELCRO.TM. strips can be used to reversibly attach the leash and collar portions. Another embodiment of the invention includes a restraint system which includes a collar assembly coupled to a leash assembly. The collar assembly and the leash assembly are made from separate straps and are attached to each other by a connecting element.

Abstract: A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal, a scan input signal, a scan enable signal, a data enable signal and a single-phase clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data or the scan signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal.

Abstract: A circuit for locally ensuring mutual exclusivity of selected signals during scan testing is coupled between an IEEE 1149.1 TAP controller and a conventional gating circuit. The mutual exclusivity circuit includes an AND-gate, an inverter, a first scan flip-flop and a second scan flip-flop. The first and second flip-flops have their scan-input leads hardwired to receive logic "1" and logic "0" signals, respectively. The first flip-flop also has its data input lead hardwired to receive a logic "0" signal. During the scan mode, the AND-gate receives a conventional rst.sub.-- tri.sub.-- en signal from the TAP controller. Thus, the AND-gate outputs a local.sub.-- rst.sub.-- tri.sub.-- en signal identical to the rst.sub.-- tri.sub.-- en signal. After the test pattern is scanned in, the rst.sub.-- tri.sub.-- en signal transitions to a logic "1" level, causing the local.sub.-- rst.sub.-- tri.sub.

Abstract: A circuit for coupling a LIC driver to a IEEE 1149.1 boundary scan implementation includes a logic circuit that converts the data and oe signals of the IEEE 1149.1 specification to test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the LIC driver. These test "q.sub.-- up" and "q.sub.-- dn" signals are selectively provided to the LIC driver during boundary scan testing of the output driver. In a further refinement, the logic circuit also converts functional q.sub.-- up and q.sub.-- dn signals provided by the circuit under test to the data and oe signals of the IEEE 1149.1 specification. The logic circuit allows the widely used IEEE 1149.1 boundary scan standard to be used with LIC drivers. The resulting compatibility simplifies the testing and use of the LIC drivers, and provides a new boundary scan standard for use with LIC drivers that is compliant with the IEEE 1149.1 standard.

Abstract: A bistable member including a bistable, invertable dish- or dome-shaped base portion and an engaging projection extending therefrom. A male member is engaged with the bistable member by pressing the male member against a central apex of the bistable member that is surrounded by the engaging projection, thereby inverting the bistable member from a first stable form to a second stable form. In the second stable form, the engaging protrusion and a portion of the bistable member wrap around a knob of the male member, thereby securing the male member to the bistable member. A subsequently applied triggering energy re-inverts the bistable member, thereby releasing the male member. This assembly is usable as a snap fastener by setting an equilibrium point of the bistable member such that a relatively large triggering energy is required to re-invert the bistable member.

Abstract: A method for coupling a linear impedance control (LIC) type output driver to IEEE 1149.1 boundary scan circuitry includes entering a boundary scan load mode to load a test pattern into a chain of boundary scan registers (BSRs). The test pattern includes values corresponding to output enable and data signals according to the IEEE 1149.1 standard. Then these data and output enable signals from the BSRs are converted into test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the LIC driver. These test "q.sub.-- up" and "q.sub.-- dn" signals are selectively provided to the LIC driver during boundary scan testing of the LIC driver. In a further refinement, the method enters a boundary scan capture mode to capture the response (i.e., the functional q.sub.-- up and q.sub.-- dn signals) of the circuit under test to input test patterns shifted into the BSRs. The functional q.sub.-- up and q.sub.-- dn signals are converted into response data and oe signals complying with the IEEE 1149.