Abstract: Methods and apparatuses to detect spectrum inversion based on estimated frequency offset in carrier signal. In one embodiment, a receiver includes an I/Q swap module to output an in-phase component and a quadrature-phase component; a frequency offset estimator to determine an offset in carry frequency of the in-phase and quadrature-phase components; and a spectrum inversion detector coupled to the frequency offset estimator and the I/Q swap module. The spectrum inversion detector is configured to signal the I/Q swap module to swap the in-phase component and the quadrature-phase component when an absolute value of the offset in carry frequency is above a predetermined threshold.

Abstract: Methods and apparatuses to perform iterative decoding of Low Density Parity Check (LDPC) codes based on selecting a lambda number of minimum values. In one aspect, an LDPC decoder is configured for: sorting a plurality of incoming messages of a check node according to magnitudes of the incoming messages; identifying a predetermined number of unique message magnitudes from the incoming messages; and computing outgoing messages for a subset of the plurality of incoming message, where the messages of the subset have different magnitudes larger than the predetermined number of unique message magnitudes but the outgoing messages are computed to have the same magnitude. In at least one example, the decoder is further configured for computing outgoing messages that have magnitudes equal to any of the predetermined number of unique message magnitudes. In general, the magnitudes computed for all outgoing messages may not necessarily be the same.

Abstract: Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.