Abstract: One aspect of the present invention includes a circuit for detecting when an input voltage exceeds a predetermined threshold. The circuit for detecting includes an input for receiving the input voltage. Further, the circuit includes a plurality of switching devices, wherein each of the switching devices comprises a first and second terminal for defining a variable conductive path, and a third terminal for receiving a signal to control said variable conductive path. The plurality of switching devices includes three switching devices. The first switching device has a first terminal coupled to the input and a second terminal coupled to a first node. The second switching device has a first terminal coupled to the first node and a second terminal coupled to a second node. Finally, the third switching device has a first terminal coupled to the second node.

Abstract: An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.

Abstract: A method and circuitry for masking data in a memory device are provided, which detect whether at least one failed bit location within the memory device is equal to a corresponding bit within input data. Data is written to the memory device as selectively inverted from the input data based upon whether the failed bit location is equal to the corresponding bit. An inversion bit within the memory device is selectively set to indicate whether the written data is inverted from the input data.

Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11).

Abstract: A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising a positive voltage switching circuit, a first isolating transistor, and a second isolating transistor. The positive voltage switching circuit may include an inverter with feedback transistor and a third isolating transistor. In one embodiment, the positive voltage switching circuit is capable of switching up to three positive voltage values and reference voltage to the wordline terminal.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: The indicator circuit and method of this invention include an OR circuit having at least two inputs and an output. A signature mode signal input is connected to one input of the OR circuit and a special test mode signal input is connected to a second input of the OR circuit. A logic circuit for providing indicator signals has at least three inputs and at least two outputs. A first input to the logic circuit is connected to the output of the OR circuit. At least one signature address signal is connected to a second input of the logic circuit. The signal indicating the results of the special test mode is connected to a third input of the logic circuit. A first preprogrammed code indicator circuit has an input connected to a first output of the logic circuit and a second preprogrammed code indicator has an input connected to a second output of the logic circuit. The first preprogrammed code indicator may contain, for example, a manufacturer code.

Abstract: In accordance with one embodiment of the invention, an integrated circuit memory capable of receiving address signals has a plurality of array banks. Each array bank has a plurality of memory cells arranged in rows and columns and has a means for addressing the rows and columns of the array banks in response to the address signals. The integrated circuit includes a means for de-coupling power from at least one array bank in response to at least one bit of an address signal.

Abstract: The structure and method of this invention provide, for example, electrical isolation between active elements in adjacent rows and/or columns of an integrated circuit by use of a self-aligned field-plate conductor formed over and insulated from the substrate regions that are bounded by the channel regions of field-effect transistors in adjacent rows and that are bounded by the bitlines forming those transistors in a column. The field-plate conductor is formed, for example, in a strip that extends over the isolation areas and thermal insulator regions between row lines of the memory cell array. The field-plate conductor strip is connected to a voltage supply that has a potential with respect to the potential of the semiconductor substrate which causes the isolation areas to be nonconductive. Component density may be increased over that of prior-art structures and methods.

Abstract: A FAMOS memory bit (40) is protected from voltage spike caused by an electrostatic discharge or otherwise by an ESD protection circuit (12). Responsive to a voltage spike on V.sub.pp, the ESD protection circuit (12) couples the drain of the FAMOS memory bit (40) to V.sub.cc or another high capacitance node.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Bitline isolation is by P/N junction or by oxide-filled trench, permitting relatively small spacing between transistors. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: An electrically-erasable, electrically-programmable read-only memory cell 10 is formed at a face of a layer of semiconductor 30 of a first conductivity type. A first source/drain region 16 and a second source/drain region 20 are formed in the face of layer of semiconductor 30 of a second conductivity type opposite the first conductivity type and spaced by a first channel area 50. A third source/drain region 18 is formed in the face of semiconductor layer 30 of the second conductivity type spaced from second source/drain region 20 by a second channel area 52. A thick insulator region 44 is formed adjacent at least a portion of second source/drain region 20 and includes a lateral margin of sloped thickness overlying a corresponding lateral margin of second source/drain region 20. The corresponding lateral margin of second source/drain region 20 has a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of thick insulator region 44.

Abstract: In one embodiment, the pulse-generating circuit includes a triggering field-effect device having a source-drain path connected between a voltage supply and an internal node and having a gate connected to a source of reference potential, a capacitor connected between the voltage supply and the output node, and a detector field-effect device having a source-drain path connected between the output node and the source of reference potential and having a gate connected to the internal node. An optional load device, an optional pull-down device, an optional second capacitor, a optional string of diode-connected devices, and an optional feedback device may be included. Device channel lengths are specified for proper operation. In one embodiment, the circuit includes only a detector field-effect transistor and a load field-effect transistor, the detector transistor having a channel length substantially longer than the channel length of the load transistor.

Abstract: A common connection to reduces the amount of chip area required to perform read and programming functions, particularly where signals such as read, programming, supply voltage and data signals are generated from remote locations on the memory chip. The common connection is made in an integrated circuit having a control circuit, a plurality of memory cell arrays having column lines, a sense amplifier circuit, and a programming circuit including at least first and second parts. At least one column of one memory cell array is selectively connected to a common line/node upon receiving at least a first signal from the control circuit. The first part of the programming circuit is selectively connected to the common line/node upon receiving a second signal from the control circuit. The second part of the programming circuit is connected to the common line/node upon receiving a third signal from the control circuit.

Abstract: A method is described for programming a semiconductor array of EEPROM cells. A selected cell is connected, by definition, to a selected source-column line, a selected drain-column line and a selected wordline. Each deselected memory cell in the array is connected to a deselected source-column line, a deselected drain-column line and/or a deselected wordline. The method includes preselecting first, second, third, fourth and fifth programming voltages such that the second programming voltage is more positive than the first programming voltage and such that the third, fourth and fifth programming voltages are intermediate between the first and second programming voltages. The first programming voltage is applied at least to a selected column line and to each of the same-type deselected column lines. The third programming voltage is applied to the selected wordline and the fourth programming voltage is applied to each deselected wordline.

Abstract: A circuit and method for rapid removal of drain-column programming voltages from drain-column lines of a memory array. The circuit includes a resistor/transistor connected between a supply voltage and a common node, the resistor/transistor being enabled by a program enable signal. During the discharge operation, the source-drain paths of a driver transistors of the array connect column lines to reference potential. The gates of the driver transistors are coupled to the common node. An enabling transistor has a source-drain path connecting reference potential to the common node and has a gate connected to the program enable signal. The circuit includes at least one inverter, an OR circuit, and a bypass transistor. The bypass transistor has a source-drain path connected between the supply voltage and the common node and a gate coupled to the common node through the inverter and the OR circuit.

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor with or without a split gate. The floating-gate transistor may have a self-aligned tunnel window of sublithographic dimension positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide and the floating gate extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in the tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches are used for electrical isolation between individual memory cells, allowing an increase in cell density.

Abstract: A charge-pump circuit implements ramp control, steady-state regulation and trimming of the negative voltage pulses. The circuit includes a negative-voltage charge-pump subcircuit having multiple phase inputs, a phase-enable input, an output, a supply voltage, a reference voltage, a ramp-control subcircuit for controlling the rate of change of the voltage at the output of charge-pump subcircuit, and an amplitude-control subcircuit for controlling the amplitude of the voltage at the output of the charge-pump subcircuit. The ramp-control has an input coupled to the output of the charge-pump subcircuit and an output coupled to the phase-enable input of the charge-pump subcircuit. The amplitude-control subcircuit has an input to the output of the charge-pump subcircuit and has an output coupled to the phase-enable input of the charge-pump subcircuit.

Abstract: A transistor structure is disclosed which has a vertical channel which has its length controllable by currently-used diffusion processes, and which occupies a minimum of silicon surface area. The transistor is constructed by using a triple-level implant and diffusion process. The drain region is diffused into the silicon area by way of ion implantation and subsequent diffusion. The channel region, of opposite conductivity-type from the drain region, is implanted and diffused into the drain region. The source region is similarly implanted, and diffused into the channel region. A trench is etched into the silicon, extending through the source, channel and drain regions; gate oxide is grown in the trench and a polysilicon gate is deposited in the trench, conformal with the gate oxide. Transistor action takes place in the channel region along the walls of the trench, dependent upon the voltage applied to the gate electrode.

Abstract: A level-shifter circuit includes a deep N-tank to insulate the N-channel portions of transistors from the substrate. The circuit is formed on a P-type substrate coupled to reference voltage Vss. A first field-effect transistor has first and second N+ doped regions formed in a third isolating P- doped region. The third doped region is formed in a fourth isolating N- doped region, which is formed in the substrate. A second transistor has first and second N+ doped regions formed in the same isolation regions as those of the first transistor. A third field-effect transistor has first and second P+ doped regions formed in an isolating N- region that is formed in the substrate. A fourth field-effect transistor has first and second N+ doped regions formed in the same isolation N- region as that of the third transistor. The gate of the first transistor is coupled to a first input.