Abstract: A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable.

Abstract: A selective low power clocking apparatus and method is used to reduce power consumption by an electronic system or integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits or functional blocks. Each sub-circuit or functional block is configured to operate under control of a clock signal and further includes an apparatus for holding or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, the clock signal to that sub-circuit is disabled. The arbiter circuit continuously monitors the system bus. Upon detecting that the external system needs to transmit or receive signals from the electronic system or integrated circuit, the arbiter re-enables the clock signal to the sub-circuits which are required for the transmission or reception.

Abstract: A method for metallizing semiconductor materials includes two processing steps. In the first step, a layer of an alloy of conductive metal, such as aluminum, and refractory metal, such as titanium, tungsten or silicon, is deposited on the surface in a single step from a single source. In the second step, a layer of the conductive metal is deposited over the alloy layer. Thus, using this method, metallization can be conveniently performed using two chambers.

Abstract: A deposition chamber used in the physical vapor deposition of wafers has a side pocket for pasting the bottom of a collimator. To prolong the useful life of a collimator it is rotated into the side pocket and the bottom is pasted with a pasting material which is resistant to cracking and flaking. A series of wafers are cycled through the deposition chamber. While each wafer is in the deposition chamber a deposition material is sputtered onto its surface. After a predetermined number of wafers are sputtered in the deposition chamber a pasting cycle is run. During the pasting cycle, a pasting material is sputtered over the deposition chamber and the top of the collimator. The collimator is then moved into the side pocket of the deposition chamber and a pasting material is sputtered from a second target over the bottom of the collimator.

Abstract: A deposition chamber includes a target and an acceptor for supporting a wafer during a deposition cycle. The acceptor is made out of a pasting material in order that a pasting cycle can be run periodically in the deposition chamber to form a barrier between the layers of the target material to prevent the layer of target material from becoming too thick and thereby cracking and flaking. A shield protects the interior of the chamber during a deposition cycle. A collimator may be present between the target and the acceptor. A plasma is formed in the chamber and selectively attracted toward the target for deposition of target material onto a wafer or toward the acceptor for pasting acceptor material onto the shield and the bottom of the collimator, if present. A plurality of wafers are cycled through the deposition chamber for depositing the deposition material on their surface.

Abstract: A self cleaning collimator is provided which avoids a buildup of deposited material such that the collimator does not become clogged, deposition rates remain constant and flakes of deposited material are not formed. The collimator is formed of a dielectric material. The collimator and the target are physically mounted in contact with one another. During a deposition process, a portion of the deposited material will unavoidably also be deposited onto the walls of the passages through the collimator. Eventually, the buildup of such deposited material will provide an electrical path from the deposited material to the target. When this occurs, the electrical path will allow the material deposited on the walls of the passages through the collimator to act as a portion of the target. This material will then be depleted as it is deposited onto the semiconductor wafer 112.