Abstract: A digital computer system has a central processor unit (CPU) and a store queue facility. The store queue facility receives full digital words or segments thereof (bytes) for intermediate storage prior to storage in an addressable unit such as a dynamic random access memory (DRAM). The store queue facility has a plurality of registers for storing digital words and bytes for storage at different, discreet addresses in the addressable unit. The store queue has circuitry for assembling bytes into a digital word or into a plurality of bytes for ultimate storage in the addressable unit. Some combinations of bytes are not valid and will therefore not be entered together in a single digital word.

Abstract: A computer system includes an accessible memory controller, an accessible cache controller, and circuitry for accessing the accessible memory controller and the accessible cache controller simultaneously. Certain preferred embodiments of the present invention also include a deassertable miss line, that is, a line which when deasserted indicates that the data was found in the cache and that the memory access should be cancelled.