Abstract: A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second processing block. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions.

Abstract: A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars.

Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.

Abstract: A method and system for an algorithm-based network snoop avoider is provided. A first data processing system and a second data processing system communicate on a physical network by transmitting data packets on the network using a virtual private network (VPN). Data packets are transmitted through a first VPN tunnel between the first data processing system with a first network address terminating a first end of the VPN tunnel and the second data processing system with a second network address terminating a second end of the first VPN tunnel. The VPN is automatically reconfigured to use alternate addresses on the network for the tunnel endpoints by automatically determining, in accordance with a predetermined algorithm, a third network address and a fourth network address and by automatically assigning the third network address to the first data processing system and the fourth network address to the second data processing system.

Abstract: A method and implementing computer system is provided for the creation of large numbers of threads in a computer system. An exemplary embodiment supports up to sixteen segments in memory of thread private data for each process or application program running on the system. Each segment contains support for 2K threads. These segments are identified in process' user structure which is located in the process private data segment of memory allowing cleanup collection on a per-segment basis. The thread's private data is composed of two parts, viz. its private kernel thread stack (96K) and uthread data structure. The uthread contains the individual data fields that are referenced only by the thread, including the register save area for the thread.

Abstract: In a searching or browsing session for Web pages on the World Wide Web (Web), a system for precluding repetitive accessing of documents linked to hyperlinks in a plurality of hypertext documents is presented. The system is directed to a Web communication network with user access via a plurality of data processor controlled interactive receiving display stations for displaying received hypertext documents of at least one display page containing text, images and a plurality of embedded hyperlinks, each hyperlink being user selectable to access and display a respective linked hypertext document. The system includes user interactive means for discounting hyperlinks in received Web documents and means for keeping track of each discounted hyperlink in each received or accessed document. The system further includes means for precluding the accessing of any document linked to a previously discounted hyperlink.

Abstract: The present invention discloses a method of managing lists in a multiprocessor system without the use of locks that prevent contention for the list. List management in a linear list with a front and a back of the list has applications where it is desirable to manage the list in a Last In First Out (LIFO) and a First In First Out (FIFO) or a combination of LIFO and FIFO. LIFO and FIFO list management can be done by restrictively adding data elements to the front, back and removing data elements from the front of a managed list. At certain times there can be contention for a list and either locking routines are in place to prevent contention or some other method is used to guarantee data element integrity. The present invention discloses a set of operations that when used with certain protocols allow two or more processors to access a list as a LIFO or FIFO in a multiprocessor system without the use of locks.

Abstract: The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis.

Abstract: A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.

Abstract: The present invention is embodied in a system and method for projecting a liquid crystal display (LCD) of a personal data assistant or mobile telephone. In general, the present invention enables users of PDAs and/or mobile telephones to enlarge the view of textual and graphical images. Namely, the present invention is embodied in a system and method that projects the LCD display screen of LCD displaying devices, such as PDAs and/or mobile telephones, onto a larger surface, for example, the back of car or airplane seat. This allows Internet information, including World Wide Web (WWW) pages or online demos with text and images to be enlarged. Also, enlargement of text and images by the projection arrangement of the present invention allows easier reading for people that have difficulty seeing small text/numerical characters and images.

Abstract: A no-integrity management method and system for managing logical volumes of a computer system. The no-integrity refers to the fact that the availability status of each partition within the mirrored logical volumes is not written to a direct access storage device but instead stored within a volatile memory. When the computer system is shutdown the availability status information is discarded, and the availability status of each partition is marked as active upon first open of a partition after startup of the computer system.

Abstract: In a search session through a browser for pages on the World Wide Web (Web), a system for precluding repetitive accessing of documents linked to hyperlinks in a plurality of hypertext documents. The system is directed to a Web communication network with user access via a plurality of data processor controlled interactive receiving display stations for displaying received hypertext documents of at least one display page containing text, images and a plurality of embedded hyperlinks, each hyperlink being user selectable to access and display a respective linked hypertext document. In addition to precluding hyperlinks which had been activated in previous pages and/or hyperlinks which have been discounted merely by having been present in previous pages, the Web browser may be setup to permit the user to specifically discount individual hyperlinks or groups of hyperlinks. Also, the Web browser may be setup to preclude repetitive hyperlinks in subsequent Web pages from searches from different search engines.

Abstract: A method of providing information about a set of interrelated objects or files on one or more servers in a computer network, such as pages on the Internet's world wide web. The method involves construction of a web links object that contains information regarding the links between the various web pages. When a user at a workstation sends a request for a specific web page (designating a particular universal resource locator), the server instead transmits the web links object to allow the user to see the hierarchy of the web site before downloading the contents of the web pages. The server can store the links object (such as one created by the web site designer), or can dynamically create a web links object upon request by analyzing the links in the various web pages. Alternatively, the workstation can perform the analysis and construct the web links object.

Abstract: The present invention is embodied in a system and method for predicting design errors, such as errors in integrated circuit design. The system and method of the present invention use a probabilistic model, such as a Bayesian Belief Network (BBN), to predict design errors at any point in the design process by using information about the current design in combination with historical design error data from previous designs. Prediction of design errors is based on a probabilistic comparison of conditions or error symptoms in the current design, to similar or identical conditions or error symptoms associated with design errors identified in prior designs.

Abstract: The present invention is embodied in a system and method for sharing input and output pins between a plurality of separate logic circuits coexisting within a single microprocessor such that the microprocessor is capable of assuming the characteristics of a desired logic circuit. The present invention achieves controlled sharing of bidirectional input and output pins without the requirement to use multiplexing logic. Because the pins may be shared among a plurality of logic circuits, a single microchip may be used for completely different purposes by enabling or disabling selected logic circuits. In other words, a single microchip can take on any number of properties by simply enabling one or more logic circuits while disabling other.

Abstract: The present invention is embodied in a system and method for recovering from design errors, such as errors in an integrated circuit design. The system and method of the present invention use a probabilistic model, such as a Bayesian Belief Network (BBN), in combination with case-based inferential reasoning to predict or detect design errors at any point in the design process by using information about the current design in combination with historical design error data from previous designs. Once conditions associated with design errors are predicted or detected, an error profile is generated. An inference engine then uses conditional probabilities produced by the probabilistic model to compile a set of exact or similar cases from a historical knowledge base containing solutions and workarounds to previously identified design errors, based on their probable relevancy to the current design case.

Abstract: The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed.

Abstract: Disclosed is an apparatus and method to build programs from activity functional units (AFUs) within a graphical environment. AFUs are comprised of a set of graphically-represented functional units (FUs). The resulting AFUs can be combined with other FUs and previously-created code represented in FU graphical form to build large complex programs which are easily modified and added to by the user by means of manipulation of graphical elements on the computer screen.

Abstract: There is provided a system for dynamically resynchronizing a storage system made up of a plurality of mirrored logical volumes respectively divided into a plurality of mirrored logical data partitions in the event of a system failure. Immediately after the correction of the problem causing the failure, meals start to resynchronize the plurality of logical volumes but without waiting for the resynchronization to be completed; means access data from a data partition in one of said logical volumes. Then there are means for determining whether the portion of the logical volume containing the accessed partition has already been resynchronized, together with means responsive to these determining means for replacing the corresponding data in the other mirrored partitions in the logical volume with the accessed data, in the event that the portion of the logical volume has not been resynchronized.

Abstract: An enhanced probe apparatus is provided for facilitating pin contact on a multi-pin integrated circuit or other high density connector-pin environment. The probe includes, in one exemplary embodiment, a magnification lens and an LED lamp which are both are mounted in various arrangements to an oscilloscope probe device. Both the lens and the LED are adjustable independently and each is movable in a plurality of directions to optimize the magnification and illumination of a pin contact area on one edge of an integrated circuit chip in order to facilitate pin identification and probe-to-pin contact for signal acquisition.