Abstract: The mechatronic vehicle safety seat described transforms the geometry of the bottom frame and backrest frame associated with a head restraint when a collision is imminent. On a signal from a pre-crash detection device, or a manual or verbal indication, an energized solenoid instantly releases the forces of torsion springs and triggers the seat bottom and backrest for concurrent movement in sufficient time to mitigate excessive accelerations, loads and moments of forces acting upon seated occupants in response to impact modes. The distorted geometry of the bottom frame and backrest with head restraint enhances the safety performance of the seat belt and reduces the aggressiveness of airbags.

Abstract: In the field of direct mind-machine interactions, prior art devices and methods do not provide sufficiently fast and reliable results. Mental influence detectors (100, 140, 400, 430) and corresponding methods provide fast and reliable results useful for detecting an influence of mind and hidden or classically non-inferable information. An anomalous effect detector (100) includes a source (104) of non-deterministic random numbers (110), a converter (114) to convert a property of numbers, a processor to accept converter output (118) and to produce an output signal (124) representative of an influence of mind. The processor output signal (124) contains fewer numbers than the input (110).

Abstract: An RNG circuit is connected to the parallel port of a computer. The circuit includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range. A low-frequency cut-off is selected to maintain high band-width yet eliminate the 1/f amplifier noise tail. A CMOS comparator with a 10 nanosecond rise time converts the analog signal to a binary one. A shift register converts the serial signal to a 4-bit parallel one at a sample rate selected at the knee of the serial dependence curve. Two levels of XOR defect correction produce a BRS at 20 kHZ, which is converted to a 4-bit parallel word, latched and buffered. The entire circuit is powered from the data pins of the parallel port. A device driver interface in the computer operates the RNG. The randomness defects with various levels of correction and sample rates are calculated and the RNG is optimized before manufacture.

Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.

Abstract: During bottom filling of high aspect ratio gaps and trenches in an integrated circuit substrate using HDP-CVD, a pulsed HF bias is applied to the substrate. In some embodiments, pulsed HF bias is applied to the substrate during etching operations. The pulsed bias typically has a pulse frequency in a range of about from 500 Hz to 20 kHz and a duty cycle in a range of about from 0.1 to 0.95.

Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.

Abstract: A ruthenium-containing thin film is formed. Typically, the ruthenium-containing thin film has a thickness in a range of about from 1 nm to 20 nm. The ruthenium-containing thin film is annealed in an oxygen-free atmosphere, for example, in N2 forming gas, at a temperature in a range of about from 100° C. to 500° C. for a total time duration of about from 10 seconds to 1000 seconds. Thereafter, copper or other metal is deposited by electroplating or electroless plating onto the annealed ruthenium-containing thin film. In some embodiments, the ruthenium-containing thin film is also treated by UV radiation.

Abstract: An accelerator solution is globally applied to a workpiece to form an accelerator film, and then a portion of the accelerator film is selectively removed from the workpiece to form an acceleration region having a higher concentration of accelerator. The higher concentration of accelerator causes metal to deposit at a faster rate in the acceleration region than in a non-accelerated region for the duration of metal deposition. To make a metal feature, a resist layer is applied to a workpiece surface and patterned to form a recessed region and a field region. Then, a metal seed layer is deposited on the workpiece surface. An accelerator solution is applied so that an accelerator film forms on the metal seed layer. A portion of the accelerator film is selectively removed from the field region, leaving another portion of the accelerator film in the recessed region.

Abstract: A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited.

Abstract: An electroplating solution contains a wetting agent in addition to a suppressor and an accelerator. In some embodiments, the solution has a cloud point temperature greater than 35° C. to avoid precipitation of wetting agent or other solute out of the plating solution. In some embodiments, the wetting agent decreases the air-liquid surface tension of the electroplating solution to 60 dyne/cm2 or less to increase the wetting ability of the solution with a substrate surface. In some embodiments of a method for plating metal onto substrate surface, the electroplating solution has a measured contact angle with the substrate surface less than 60 degrees.

Abstract: A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited.

Abstract: Carbon monoxide gas is provided in a ruthenium-deposition apparatus to clean undesired ruthenium-containing deposits from apparatus surfaces. Carbon monoxide gas is mixed with reactant gases in apparatus tubing and in a ruthenium-deposition reaction chamber to inhibit formation of undesired ruthenium deposits on apparatus surfaces and to remove ruthenium deposits.

Abstract: An RNG circuit is connected to the parallel port of a computer. The circuit includes a flat source of white noise and a CMOS amplifier circuit compensated in the high frequency range. A low-frequency cut-off is selected to maintain high band-width yet eliminate the 1/f amplifier noise tail. A CMOS comparator with a 10 nanosecond rise time converts the analog signal to a binary one. A shift register converts the serial signal to a 4-bit parallel one at a sample rate selected at the knee of the serial dependence curve. Two levels of XOR defect correction produce a BRS at 20 kHZ, which is converted to a 4-bit parallel word, latched and buffered. The entire circuit is powered from the data pins of the parallel port. A device driver interface in the computer operates the RNG. The randomness defects with various levels of correction and sample rates are calculated and the RNG is optimized before manufacture.

Abstract: In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.

Abstract: An excited surfactant species is created by generating plasma discharge in a surfactant precursor gas. A surfactant species typically includes at least one of iodine, led, thin, gallium, and indium. A surface of an integrated circuit substrate is exposed to the excited surfactant species to form a plasma-treated surface. A ruthenium thin film is deposited on the plasma-treated surface using a CVD technique.

Abstract: A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.

Abstract: A low-k precursor reactant compound containing silicon and carbon atoms is flowed into a CVD reaction chamber. High-frequency radio-frequency power is applied to form a plasma. Preferably, the reaction chamber is part of a dual-frequency PECVD apparatus, and low-frequency radio-frequency power is applied to the reaction chamber. Reactive components formed in the plasma react to form low-dielectric-constant silicon carbide (SiC) on a substrate surface. A low-k precursor is characterized by one of: a silicon atom and a carbon—carbon triple bond; a silicon atom and a carbon—carbon double bond; a silicon—silicon bond; or a silicon atom and a tertiary carbon group.

Abstract: Hermetic amorphous doped silicon carbide is deposited on an integrated circuit substrate in a PECVD reactor. Nitrogen-doping of an SiC film is conducted by flowing nitrogen-containing molecules, preferably nitrogen or ammonia gas, into the reactor chamber together with an organosilane, preferably tetramethylsilane, and forming a plasma. Oxygen-doping is conducted by flowing oxygen-containing molecules into the reaction chamber.

Abstract: An improved method and apparatus for microwave imaging of an inhomogeneous target, in particular of biological tissue, compensates for the interactions between active antennae and nonactive antennae. Measured electric field data are processed in magnitude and phase form so that unwrapped phase information may be used directly in the image reconstruction. Initial finite element measurements and calculations are used to determine the perimeter dimensions of the target being examined, resulting in more accurate image reconstructions. An improved regularization technique is a hybrid of a Marquardt regularization scheme with a spatial filtering technique and a Tikhonov regularization scheme. An improved switching matrix enables simultaneous sampling of electric field data from a plurality of receiving antennae.

Abstract: A hydrogen-containing chemical species is included in the reactant gas mixture in a plasma-enhanced CVD process for forming a carbon-containing dielectric film. The CVD reactant gas mixture contains silicon, oxygen, hydrogen and carbon atoms for forming a novel carbon-containing silicon oxide film in which both Si—C and Si—H bonds are present. Because dielectric material deposited in accordance with the invention has a significant number of Si—H bonds, which are more robust than Si—C bonds, it is more resistant to undesired etching and other physical changes during fabrication than dielectric material formed by conventional methods. A method in accordance with the invention allows a faster deposition rate. A dielectric film formed in accordance with the invention has enhanced uniformity characteristics and a dielectric constant less than 3.