Abstract: Circuitry for providing unlimited, self-adjusted drive current and suitable for power applications is described. A four terminal high efficiency, high gain driver circuit including enabling circuitry is provided along with a positive feedback loop that is designed to provide unlimited drive current which automatically adjusts to the load requirement. The drive circuit includes a startup transistor, drive regulation transistors, predrive transistors, a driving or output transistor, and a current splitter. The drive regulation transistors and the current splitter provide a positive feedback loop which supplies current to the predrive transistors and the driving transistor. Under typical loading conditions, feedback loop operation will cause the collector to emitter voltage of the driving transistor to decrease which causes the drive regulation transistors to saturate. This condition decreases positive feedback loop drive which in turn regulates the predrive current to the level required by the load.

Abstract: A horizontal structure transistor is fabricated in a shallow epitaxial island which is completely surrounded by an insulator, such as oxide. The transistor has base and emitter regions which are diffused into the island from the same mask so that the base width is controllable and remains constant with respect to the emitter. A polysilicon base contact rests on top of the island and is isolated from the emitter and collector regions by an oxide layer. The horizontal structure transistor can easily be fabricated to include complementary bipolar transistors and complementary IGFET devices on the same substrate.

Abstract: A system and method for forming a pattern, such as a layer of metallization, on a surface. A layer comprising patterning material is positioned next to a deposition surface and a portion of the layer is heated to deposit some of the patterning material on the surface. The invention provides a means for transferring a pattern under atmospheric temperature and pressure conditions.

Abstract: A dynamic RAM cell of the contactless type with a buried N+ source/drain region is constructed by the metal-gate non-self-aligned technique. A lightly-doped drain is provided by employing both arsenic and phosphorus in the buried N+ region. The effects of impact ionization are thus minimized, and a high density cell array is provided.

Abstract: The disclosure relates to a process station to precisely control the electrochemical anodization of specially prepared silicon substrates. Remotely placed voltage probes are utilized to monitor changes in the potential drop across the wafer as the anodization proceeds. As the available anodilizable area changes, the voltage drop across the wafer and hence the anodization current density is maintained at the desired value by the computer through the use of active feedback provided by these probes. Any desired anodization conditions can be programmed into the system using the system software, thereby adding an even greater degree of control over the process.

Abstract: A method for making integrated circuits in which a polyimide/conductor multilevel film (17) in cast on a substrate (10), using available or existing semiconductor processing equipment. The polyimide film (17) is formed from readily available polyamic acid resins, and the conductor (16) can be sputtered aluminum formed to interconnection conductor patterns (16,16-) by standard photolithographic techniques. After fabrication of the multilayer film (17), the conductors (16,16') of the film (17) and the device circuit (30) are brought into aligned contact, and the device circuit (30) affixed to the film (17). The film (17) and the device circuit (30) are then removed from the substrate (10) for further processing, such as bonding the device and film to a mother board or leadframe, as desired.

Abstract: Circuitry for controlling the operation of a transient voltage compensation circuit is disclosed. An input buffer circuit 10 is provided which includes a phase splitter transistor 30 having a base at which input signals are applied and an emitter which is coupled to internal ground through Schottky diode 32. A compensation circuit 12 prevents the undesirable switching of transistor 30 during fluctuations in the internal ground voltage level by drawing current from the base of transistor 30 through transistor 42 which has a base connected to a source of current and an emitter connected to internal ground. Transients in the internal ground level effect the turn on of transistor 42 which prevents the turn on of transistor 30 under low input voltage conditions. A compensation control circuit 11 is provided to disable compensation circuit 12 under high input voltage conditions yet allow its normal operation when a low voltage level is applied at the input.

Abstract: A process for forming a topside substrate contact in a trenched semiconductor structure. A trench (24, 26) is etched into a P- block of substrate (10) material. The trench (24, 26) is filled with silicon dioxide, and then the substrate material (10) circumscribed by the trench (24, 26) is removed to form a well. A subcollector (48) is implanted in the well of the P. substrate. Epi material (50) is grown in the well to the top of the silicon dioxide-filled trench. A device (59) is formed in the epi (50). Ohmic contacts (70) are formed on the topside of the substrate to the device (59) within the well, and to the P- substrate itself outside the trench.

Abstract: An automated assembly line is controlled by a computer system. The assembly line is comprised of a plurality of machines which are each segmented into its basic unit operations providing work stations. The work stations are then controlled by the computer system and operated asynchronously with respect to the other work stations of the assembly line.

Abstract: A static row driver for an array of memory cells which includes a plurality of NAND gates each having a pair of row line driver input signals, an inverter coupled to an output of each of the NAND gates, a switch coupled to an output of each of the inverter circuits and a switch control coupled to each of the switches for opening an associated switch and passing the signal from a corresponding inverter output to an associated row line.

Abstract: A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the multiplier array (116) are fed back to the multiplier (48) to avoid delays associated with the remainder of the multiplier circuitry. The correction generator (122) which performs a subtraction of the product output form the multiplier array (116) from a constant, is disposed between the multiplier array (116) and the converter/rounder (52). Hence, the subtraction necessry to compute the next estimate may be performed in parallel with other multiplications, further reducing the time necessary to perform the calculation. Compare circuitry (120) is operable to compare the final approximation with an operand to quickly determine the direction of rounding.

Abstract: A semiconductor dynamic memory device is disclosed which contains circuitry for implementing both page mode and nibble modes using a conductor level selection. A clock voltage used in column decoding and output is either coupled to or decoupled from the column strobe or CAS input by conductor, so this clock voltage is rendered either dependent on, or independent of, the cycling of the column strobe.

Abstract: A semiconductor read/write memory device has a normal mode of operation and a test mode. The test mode allows concurrent writing to a number of cells in the cell array so that test patterns may be rapidly loaded. The cell array is split into subarrays and the column addressing circuitry is arranged to provide a maximum of spacing between the cells that are concurrently written. In this manner, pattern sensitivity tests may be run at higher speed because a number of bits at widely spaced positions in the array can be tested simultaneously.

Abstract: The described embodiment of the present invention provides a method and device for cleaning the surface of a silicon wafer using dry gases. At least one of the gases provided is excited by passing the gas through a microwave plasma generator or by heating the wafer thereby exciting the gases near the surface of the wafer. The excitation of the gases causes chemical reactions similar to those induced by ionization of the nongaseous cleaning materials in water. After a suitable etching period, the etching chamber is purged using an insert gas, such as nitrogen, which helps carry away the remaining reacted contaminants.

Abstract: A multiplexer (76) for coupling selected instruction word bits to a microcode memory (22) as entry point addresses. The multiplexer (76) receives sixteen bits from an instruction word register (10) and, for normal word formats, couples the opcode (40) portion unchanged to the memory (22) as an entry point address. For special instruction word formats, various bits of the instruction word fields form an entry point address, while other bits are modified and coupled to memory (22) as column addresses to access selected memory sections.

Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).

Abstract: A modular logic circuit is disclosed, where each of the modules may be selected for testing by means of a scan path within the module made up of serial register latches (SRLs), each SRL being connected to predetermined nodes in the module functional circuitry. Each of the modules has a test port, which is independent from the system bus interconnections in the logic circuit, and which has an SRL for receiving serial data for selection of the scan path within the module. Responsive to the logic state stored in a module's selection SRL, the scan path within the module will either be enabled or disabled. After selection of a module or modules for testing, serial data is scanned into the SRLs in the scan path for setting the associated predetermined functional circuitry nodes; after exercise of the functional circuitry, the SRLs in the scan path store the results of the exercise at the predetermined nodes.

Abstract: A plasma dry etch process for trench etching in single slice RIE etch reactors wherein a selective sidewall passivation is accomplished to control the profile of the trench being etched. The process comprises methods of passivating the sidewall by passivation on a molecular scale and by passivation by a veneer type passivation comprising buildup of a macroscopic residue over the surface of the sidewall. Several methods are disclosed for forming and shaping the passivating layers (both mono-atomic and bulk). By carefully controlling the composition and shape of the sidewall passivating veneer in conjunction with other etch factors, the desired trench profiles can be achieved.

Abstract: The specification discloses output buffer circuitry (10) for providing selected output driving characteristics. A plurality of input terminals (13, 24 and 30) receive control and data signals. A plurality of interconnected driver transistors (20, 28, 36 and 42) are connected to an output terminal (22). Drive selector circuitry (16, 18, 38 and 40) is connected between the input terminals (13, 24, and 30) and is responsive to the control signals to vary the electrical interconnection of the driver transistors (20, 28, 36 and 42). The output driving characteristics presented to the output terminal (22) are variable in response to the control signals.

Abstract: A high speed interstage STL buffer (27) is disclosed having a low threshold and high driving capability. A first Schottky-clamped grounded emitter transistor (28) receives input signals through a Schottky steering diode (38) and inverts the input signal. The input signal is applied in parallel through a Schottky steering diode (20) to a second Schottky-clamped grounded emitter transistor (12). The collector (22) of the second transistor (12) provides an output of the buffer (27) for driving load current in one direction with respect to the buffer output. A third transistor (40) connected as an emitter follower has the emitter (42) thereof connected to the buffer output for driving load currents in the other direction. The base (46) of the emitter follower transistor (40) is coupled by a Schottky steering diode (50) to the collector (32) of the first transistor (28).