Abstract: An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt.

Abstract: An integrated semiconductor module of reduced impedance and method utilizing a given chip architecture of the type having a memory circuit and a plurality of off-chip drivers and their I/O pads, the module being constructed in a configuration for operation of said memory circuit with less than the number of available drivers such that there are a number of excess drivers and output pads not used for driver operations, and one or more of these excess drivers and their pads are connected to the power terminals of the chip to provide one or more power paths through these drivers and their associated pads in parallel with the power paths of the operational drivers, and the method includes connecting the excess drivers and their output pads to the power terminals of the chip during its fabrication in a manner to provide additional power paths.

Abstract: A noise limited, video, digital to analog converter having an output transition time control with multiple discrete transition times. This is accomplished by a DAC control circuit in which the slew rate of the current is controlled by providing set current levels in the inverters that drive the DAC output current switches thus limiting the current available for charging and discharging the capacitance on the nodes which control the output signal. Additional control is provided by voltage clamping of these nodes which reduces the input voltage to the analog output and results in a cleaner output waveform.By so regulating and controlling the charging and discharging of these nodes, the variations in operation of the circuit due to the process used to produce the circuit in integrated form as well as temperature and supply voltage are further substantially reduced.

Abstract: An MR head circuit including a differential amplifier, means for applying a dc bias to the head, a capacitor mounted in parallel to the head to eliminate the dc voltage offset, and a feedback loop configured for evaluating the differential voltage and for controlling the current in portions of the amplifier to rapidly charge the capacitor upon circuit activation. The feedback loop also includes a thermal asperity compensator configured for producing a given signal, both upon activation of the circuit and when the magnitude of the voltage differential exceeds a given value, and the feedback loop includes means responsive to the given signal for altering select current paths of the feedback loop to thereby produce elevated charging currents in the differential amplifier during initial activation, and to increase the ac gain of the feedback loop at other times so as to raise the lower corner frequency of the differential amplifier to filter out the relatively low frequency of a thermal asperity waveform.

Abstract: A memory module configured such that it can be operated as a first memory module such as a (Single In-line Memory Module) SIMM or as a second memory module such as a (Dual In-linc Memory Module) DIMM module without requiring external switching circuitry. This is accomplished by providing a memory module card with a circuit thereon that is designed to emulate a DIMM module when plugged into a DIMM socket as found in the latest computer architectures and to emulate a SIMM module when plugged into a SIMM socket as found in older computer architectures. The memory module is provided with memory devices (DRAMS or SDRAMS) and interconnecting bypass devices (CMOS transistor pairs) mounted thereon.

Abstract: A printed circuit card having first and second circuit units mounted thereon in connection to terminal pads adjacent two card edges, with the first and second circuit units being in connection to each other and to select pads of a first edge such that upon insertion of that edge into a given card socket, both circuit units are enabled, and the circuit units also being in connection to the pads of a second edge such that upon insertion of that edge into a second card socket, only the second circuit unit is enabled. In the preferred embodiment, the card is a memory module card having buffer and memory circuit units designed to cooperate with each other and with either of standard, buffered or unbuffered memory card sockets in a system board in accordance with insertion of a first or second pad edge in one of the card sockets to automatically provide, either combined circuit unit operation, or single circuit operation. The invention is also applicable to clocked register circuits and series pass devices.

Abstract: The disclosed invention provides a circuit and burn-in test method for semiconductor devices that increases the speed of burn-in tests. The present invention accomplishes this by causing each of the devices under test to be tested multiple times (from 2 to 32+ times) during each power cycle. By such multiple cycling of the unit under test, during the power cycle, the total test time is shortened. It has also been found that the devices tested in accordance with the present invention are more efficiently stressed and have a reliability greater than devices passing the prior art tests. In accordance with the invention, the memory or logic devices under test are provided with a respective clock means that will operate each of the devices under test through multiple (from 2 to 32+ times) write and read operations during each power cycle. Data coherency for each read operation is provided as is the inversion of data if any fail is recorded during a read operation.

Abstract: A circuit card unit comprising a memory card and attached heat exchanger comprising a thin, flexible, laminated strip of foil clad plastic, or wire mesh, affixed in thermally conductive contact to each card module and extended therefrom to facilitate removal of heat from the modules. In some embodiments, the exchanger strip extends from the modules on one side of the card to those of the other side in a self supporting, heat exchanger loop spaced over the memory card. In a somewhat more compact embodiment, the strip extends from modules on one card face, along the card itself, to the modules of the other card face. In a still further embodiment, the heat exchanger strip extends from the modules of the card to a heat sink such as the housing of the computer. Additionally, the heat exchanger strips may also function as a carrier for an identifying label printed on, or attached to, the planar surface of the strip.

Abstract: This discloses a memory module adapter card that allows newer dual in-line memory modules (DIMMs) to be used by computer system boards that were built to use older single inline memory modules (SIMMs) thereby permitting computer owners to update and upgrade older machines without modifying or changing their system boards. This memory module adapter card is designed to connect a memory DIMM inserted into a DIMM socket, carried thereon, to a pair of smaller SIMM sockets on a computer system board such that the DIMM appears to the computer as a pair of the smaller SIMMs that the board was originally designed for. This decreases the need for manufacturing and maintaining an inventory of the older SIMMs and provides owners of older computers the means to extend the useful life of their existing computer system even if the SIMMs designed for the computer no longer exist or are prohibitively expensive or very difficult to locate.

Abstract: A lead frame having a plurality of metallic conductors with each conductor having a coined or stamped region near its proximal end but spaced therefrom to provide pressure points to assure substantial even joining of the conductor to semiconductor chip via an insulative adhesive medium. The lead frame, when mounted on the active face of a semiconductor chip, has wires connecting terminals on the major active surface of the semiconductor chip to the bands on selected lead frame conductors. The lead frame on the semiconductor chip and the wires which connect the semiconductor chip terminals to the bands of selected lead frame conductors are then encapsulated with a suitable insulative material to form a semiconductor module or package.

Abstract: This discloses a probe structure which does not rely on cantilevered wire and which has improved and controlled contact pressure between the probe tip contacts and the I/O pads on a semiconductor chip and which comprises a plurality of conductive contact electrodes, electrically coupled to respective leads, formed on a film stretched across a respective plurality of through holes established in a substrate. The through holes and the contact electrodes are aligned with one another and both positionally match selected I/O pads existing on a semiconductor chip to be probed. Also disclosed is a probe utilizing means connected to each one of the holes to control the pressure in the holes and between the probes and any contact on a device in contact with the probe.

Abstract: An improved, high performance differential voltage regulator for high capacitance loads using a transistor-capacitor that will, while operating with voltages below 5 volts, have wide bandwidth, high current, and loop stability over a to a wide range of output capacitive loads.The regulator achieves this through first and second control loops coupled to a first one of a pair of differential transistors 2.

Abstract: An integrated high-performance decoupling capacitor, formed on a semiconductor chip, using the substrate of the chip itself in conjunction with a metallic deposit formed on the presently unused chip back surface and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor in close proximity to the active circuit on the chip requiring such decoupling capacitance.Specifically the present invention achieves this desirable result by providing a dielectric layer on the unused backside of the chip and forming a metal deposit on the formed backside dielectric layer and an electrical connection, between the metallic deposit and the active chip circuit via a through hole in the chip.

Abstract: An integrated circuit capacitor device that increases capacitance without proportionately using more substrate surface area. Uniquely, the capacitor uses up to all four sides of the first charge plate to store charge by surrounding it with a second charge plate with an insulator layer separating the two plates.

Abstract: A fixture having an open ended housing cavity defined by an inwardly inclined wall, and including at least one moveable segment having an inwardly facing wall which defines one wall of a stack cavity configured for receiving a plurality of circuits chips positioned one over another for bonding together in a stack configuration, and an outwardly facing wall of the segment is inclined at the angle of the inclined wall of the housing and arranged in mating relation therewith such that when the segment is moved in one direction along the inclined wall of the housing, it will be urged inwardly to align the circuit chips within the stack cavity, and when urged in an opposite direction it can move outwardly to expand the stack cavity for loading and unloading.

Abstract: This discloses a probe structure which does not rely on cantilevered wire and which has controlled contact pressure between the probe contacts and the I/O pads on a semi-conductor chip and which comprises a plurality of conductive contact electrodes, electrically coupled to respective leads, formed, on a film stretched across a respective plurality of cavities established in a substrate. The cavities and the contact electrodes are aligned to one another and both positionally match selected I/O pads existing on a semi-conductor chip to be probed.Also disclosed is a probe utilizing a cantilevered, metalized oxide tongue extending across a cavity.

Abstract: The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures. Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

Abstract: These desirable results and other objects of the present invention are realized and provided by depositing coating material on a front surface of a rotating wafer to spread a thin film over this surface while directing a light positive pressure of clean gas over the backside of the spinning wafer to preclude deposits of gas borne particles of the coating material thereon.

Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

Abstract: This is an integrated timing circuit which can be formed on a microprocessor chip. The circuit uses an oscillator having a delay line and a variable delay element. The delay line and the delay element vary together to hold the velocity of signal propagation in the circuit substantially constant. The output, of the oscillator is coupled to one input of a comparator circuit. A series of inverter circuits, each of which has a respective variable delay are connected to the input of the oscillator and to a second input of the comparator circuit such that the comparator circuit senses the difference between the output signal of the inverter series and the output signal of the oscillator circuit to provide an error signal proportional to the sensed difference. A feedback loop is provided, to the variable delay means in said oscillator and to the inverter circuits to correct for the sensed difference, to establish a uniform and stable time standard at the output of the oscillator.