Abstract: A process and structure for forming an optical subassembly in an integrated circuit, comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.

Abstract: A process for milling copper metal from a substrate having an exposed copper surface includes absorbing a halogen gas onto the exposed copper surface to generate reaction products of copper and the halogen gas; removing unreacted halogen gas from the surface; and directing a focused ion beam onto the surface to selectively remove a portion of the surface comprising the reaction products.

Abstract: A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.

Abstract: A method for fabricating a heterojunction bipolar transistor having collector, base and emitter regions is disclosed. In an exemplary embodiment of the invention, the method includes forming a silicon epitaxial layer upon a substrate, the silicon epitaxial layer defining the collector region. An oxide stack is formed upon the silicon epitaxial layer and a nitride layer is then formed upon the oxide stack. Next, an emitter opening is defined within the nitride layer before a base cavity is formed within the oxide stack. The base cavity extends laterally beyond the width of the emitter opening. A silicon-germanium epitaxial layer is grown within the base cavity, the silicon-germanium epitaxial layer defining the base region. Finally, a polysilicon layer is deposited upon said silicon-germanium epitaxial layer, the polysilicon layer defining the emitter region.

Abstract: A silicon oxynitride (SiON)/silicon dioxide (SiO2) optical waveguide switch with a wavelength locked feedback control loop which monitors the wavelength of UV radiation produced by a UV tunable laser diffraction grating write source which has passed through a UV bandpass filter and is then used to selectively write a diffraction grating in the optical waveguide switch. The diffraction grating structure can be switched on or off at will, resulting in an optical switch element for IR radiation traveling through the optical waveguide. This optical switch element is a basic building block which can be used for many other systems, such as optical logic gates or all-optical cross connect switches for wide area networks. Further, it may be used to selectively tap off a portion of the optical signal, for example to read header information in a data stream (or packets) which indicates the destination switch port of the optical data, without disrupting the remaining optical data.

Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

Abstract: Electrically switchable optical elements, such as application specific integrated elements including filters, lenses and switches, are combined with wavelength locked feedback loops. Electrically Switchable Bragg Grating (ESBG) technology is combined with a wavelength locked feedback loop to provide variable focal length optical systems which automatically adjust the focal length of incident light.

Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.

Abstract: An apparatus performs source operand dependency analysis, perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single machine cycle. The apparatus first provides an enhanced means for rapid pipeline recovery due to a mispredicted branch or other store/load conflict or unsupported store/load forward circumstances. Second, the apparatus provides an improved instruction scheduling means wherein the oldest instructions that have all of their dependencies resolved are executed first. Third, the apparatus provides a means for enabling any execution or memory access instruction to execute out-of-order. Fourth, the apparatus provides a means for handling precise recovery of interrupts when processing instructions in out-of-order sequence.

Abstract: A programmable serializer comprising a multi-bit input port, a multi-bit output port, at least one multiplexer and at least one programmable address counter corresponding to the multiplexer for generating a sequence of multiplexer data input addresses that are inputted into the multiplexer address input. The multiplexer has an output connected to the multi-bit output port, an address input and a plurality of data input channels having addresses. Each data input channel is connected to a corresponding bit of the multi-bit input port. At least one data input channel is coupled to the multiplexer output when the corresponding address of the data input channel is applied to the address input. The programmable address counter receives and stores an initial address value, an address increment value and a count value and generates a sequence of addresses based on these values. The initial address value represents the multiplexer data channel that is to be initially coupled to the multiplexer output.