Abstract: A method for adjusting a clock for a jitter sensitive circuit begins by determining a low noise phase region of a primary clock. The method then continues by adjusting phase of an auxiliary clock such that a transition of the auxiliary clock falls within the low noise phase region of the primary clock to produce an adjusted auxiliary clock.

Abstract: Testing of a system-on-a-chip having a programmable section and a plurality of high-speed interfaces begins by configuring the programmable section to support a 1st level testing of the plurality of high-speed interfaces. The testing continues by testing one of the plurality of high-speed interfaces at the 1st level of testing via the programmable section. The testing continues by evaluating the tested performance characteristics in accordance with the prescribed performance characteristics of the standard to determine whether the one of the plurality of high-speed interfaces conforms with the standard requirements. When the one of the plurality of high-speed interfaces conforms with the standard requirements, the plurality of high-speed interfaces are configured for a 2nd level testing, where the 1st level testing is more stringent than the 2nd level testing. The testing continues by testing, at the 2nd level, remaining ones of the plurality of high-speed interfaces.

Abstract: A phase adjustment module in a voltage controlled oscillator (VCO) samples a VCO oscillation to detect changes in the oscillation frequency and produces a corresponding correction voltage that is feedback to the VCO input to correct the frequency change. A plurality of sampling modules, each formed to start sampling at a different point on the oscillation cycle, charge a sampling module capacitor over the period of a full oscillation cycle. The samples are coupled to a low pass filter to produce a running average of all the samples. The charge on each capacitor is coupled to a first input of a plurality of operational amplifiers and the running average is coupled to a second input. The summed output of the operational amplifiers is substantially equal to a difference between the running average and a voltage representing the instantaneous time change or phase change of the oscillation frequency.

Abstract: An SRAM cell eliminates the p-channel pull-up resistors to decrease its physical size. A tracking circuit generates a control signal used to ensure that the memory state is preserved during the idle state. The control signal controls the wordline voltage during the idle state to vary the leakage through the access transistors to ensure that current into the node through the access device is not exceeded by leakage current out of the output nodes through the storage devices. The tracking circuit control signal can also be used to vary the well to substrate bias voltage of the storage devices to decrease the leakage through the storage devices. The control signal can also be used to bias the supply rail voltage to which the storage devices are directly coupled to decrease the amount of leakage through the storage devices.

Abstract: A circuit and a method for limiting a voltage to a specified value (e.g., a rail voltage) without clipping thereby includes a pair of MOSFETs that turn on when a specified bias voltage is reached to either add to or sink current from the input node of the resistive load responsive to fluctuations in current going through the output resistive load to maintain a constant current through it. A plurality of biasing circuits is provided that control the turn on voltage levels for the MOSFETs to achieve the desired operation. The biasing circuits include circuit components that are matched to circuit components within the circuitry that adds and drains current to the output resistive load including a resistive load that matches the output resistive load.

Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

Abstract: A load management system includes a load management control center, at least one power management termination system, a plurality of power line nodes, and a plurality of load management devices. This system is operable so that the load management control center may independently, or as a group, control each of the load management devices. According to one aspect of the present invention, the load management control center accesses the load management devices across a communication network that includes a power line network. The load management devices may be addressed individually. Alternately, the load management devices may be addressed as a group or set of groups by the load management control center during load shedding operations. Load management devices may include meters that are communicatively coupled to the load management control center.

Abstract: A circuit and a method for limiting a voltage to a specified value (e.g., a rail voltage) without clipping thereby includes a pair of MOSFETs that turn on when a specified bias voltage is reached to either add to or sink current from the input node of the resistive load responsive to fluctuations in current going through the output resistive load to maintain a constant current through it. A plurality of biasing circuits is provided that control the turn on voltage levels for the MOSFETs to achieve the desired operation. The biasing circuits include circuit components that are matched to circuit components within the circuitry that adds and drains current to the output resistive load including a resistive load that matches the output resistive load.