Patents Represented by Attorney Tom Devine

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  • Error correction code pipeline for interleaved memory system
    Patent number: 5335234
    Abstract: A data stream process pipeline and method of transferring data from a storage device to a central processor unit (CPU) or cache memory includes an input latch arrangement, error correcting circuitry, and an output latch arrangement. In embodiments of the present invention the input and output latch arrangements include two latches and means for multiplexing the outputs of the two latches.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: August 2, 1994
    Assignee: Dell USA, L.P.
    Inventors: Keith D. Matteson, Michael L. Longwell