Abstract: Briefly, in accordance with an embodiment of the invention, a frequency selective surface (FSS) structure and a method is provided. The FSS structure may include a first conductive plate over a first surface of a substrate. The FSS structure may further include a first printed inductor over the first surface of the substrate and coupled to the first conductive plate. The method may include forming a frequency selective surface by patterning a first conductive material over a surface of a substrate to form a printed inductor.
Abstract: The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures. Combining ferroelectric polymer and ferroelectric oxide layers on the pre-fabricated silicon substrate cavity forms a multi-rank structure.
Abstract: The invention relate to a damascene chalcogenide memory cell structure. The damascene chalcogenide memory cell structure is fabricated under conditions that simplify previous process flows. The damascene chalcogenide memory cell structure also prevents volatilization of the chalcogenide memory material.
Type:
Grant
Filed:
April 17, 2003
Date of Patent:
September 28, 2004
Assignee:
Intel Corporation
Inventors:
Chien Chiang, Jong-Won Lee, Patrick Klersy
Abstract: A polymer memory device includes two organic adhesion layers that facilitate an integral package comprising a lower and an upper electrode and the ferroelectric polymer memory structure. The ferroelectric polymer memory structure includes crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure includes spin-on and/or Langmuir-Blodgett deposited compositions.
A memory system allows the polymer memory device to interface with various existing hosts.
Abstract: Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include a phase change material having a bottom portion, a lateral portion, and a top portion. The phase change memory may further include a first electrode material contacting the bottom portion and the lateral portion of the phase change material and a second electrode material contacting the top portion of the phase change material.
Abstract: An integrated circuit (IC) has a number of memory cells, each of which has a diode structure coupled between a bitline and a wordline that are selected when programming that cell. A target memory cell of the IC is programmed while simultaneously floating a number of unselected bitlines and wordlines in the IC.
Type:
Grant
Filed:
June 29, 2001
Date of Patent:
October 8, 2002
Assignee:
Intel Corporation
Inventors:
Daniel Xu, Tyler A. Lowrey, David L. Kencke