Abstract: Presented are ways to address the problem of replication competent adenovirus in adenoviral production for use with, for example, gene therapy. Packaging cells having no overlapping sequences with a selected vector and are suited for large scale production of recombinant adenoviruses. A method of the invention produces adenovirus incapable of replicating. The method includes a primary cell containing a nucleic acid based on or derived from adenovirus and an isolated recombinant nucleic acid molecule for transfer into the primary cell. The isolated recombinant nucleic acid molecule is based on or derived from an adenovirus, and further has at least one functional encapsidating signal, and at least one functional Inverted Terminal Repeat. The isolated recombinant nucleic acid molecule lacks overlapping sequences with the nucleic acid of the cell.

Abstract: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

Abstract: This invention is directed to a whip arm mounting (26) of the European style whip arms on the control head (10) of a dental delivery system, where multiple whip arms (26) are automatically centered and returned to the center rest or storage position without touching the control head cover (12), or the bottom pan (11), and are movable from side to side while carried in a single mounting bracket (50) in the control head.

Abstract: An oximetry sensor comprising a foam wrap member including a fastener, back film mounting member, LED assembly and photodiode connected to a cable, support rings for the LED assembly and photodiode, window film for the LED assembly and photodiode, and a top liner.

Abstract: A semiconductor device package is formed with a lead frame including a plurality of lead members positioned in an array, and a semiconductor die is secured to the lead frame. At least one pair of bus bars is connected to the lead frame and positioned over the semiconductor die, with the bus bars including a plurality of inner-digitized bond fingers. The inner-digitized bond fingers are formed from a series of alternating projections and recesses on each bus bar. A plurality of bond wires electrically couples the lead members to the semiconductor die. Other bond wires electrically couples the inner-digitized bond fingers of the bus bars to the semiconductor die. The bond wires attached to the inner-digitized bond fingers have a substantially uniform loop height and length, providing for easier manufacture and inspection of the semiconductor device package.

Abstract: A method of fabricating a substantially smooth-surfaced anti-reflective coating on a semiconductor device structure including generating a plasma from an inert gas in a process chamber in which the substantially smooth anti-reflective coating is to be deposited. The anti-reflective coating may be a dielectric anti-reflective coating (DARC) which includes silicon, oxygen and nitrogen, and is preferably of the general formula Si.sub.x O.sub.y N.sub.z, where x equals 0.40 to 0.65, y equals 0.02 to 0.56 and z equals 0.05 to 0.33. Preferably, x+y+z equals one. The method may also include fabricating a silicon nitride layer over the anti-reflective coating. A semiconductor device which includes a silicon nitride layer over an anti-reflective coating that has been fabricated in accordance with the inventive method has a density of less than about 40,000 particles or surface roughness features in the silicon nitride of about 120-150 nanometers dimension per eight inch wafer.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers wherein a first doped and activated polysilicon layer (either n-type and-p-type) is patterned on a substrate. An isolation material layer is formed abutting the first doped and activated polysilicon layer in the corners formed at the junction between the first doped and activated polysilicon layer and the substrate. A second doped and activated polysilicon layer (either n-type or p-type) is applied over the first doped and activated polysilicon layer and the isolation material layer. The second doped and activated polysilicon layer is planarized to the height of the first doped and activated polysilicon layer. The first and second doped and activated polysilicon layers are etched to substantially bifurcate the first and second doped and activated polysilicon layers. Further processing steps known in the art are utilized to complete the MOS device.

Abstract: A method and apparatus for testing unpackaged semiconductor dice having raised contact locations is disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the contact location. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations contact pad. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

Abstract: A vertically mountable semiconductor device including a plurality of bond pads disposed proximate to a single edge thereof. The bond pads are bumped with an electrically conductive material. The semiconductor device may also include a support member. Alternatively, the semiconductor device may be laminated to one or more adjacent semiconductor devices. The present invention also includes a method of attaching the semiconductor device to a carrier substrate. Preferably, solder paste is applied to terminals on the carrier substrate. The semiconductor device is oriented vertically over the carrier substrate, such that the bumped bond pads align with their corresponding terminals. The bumps are placed into contact with the solder paste. The bumps and solder paste are then fused to form a joint between each of the bond pads and respective terminal, establishing an electrically conductive connection therebetween and imparting structural stability to the semiconductor device.

Abstract: The present invention relates to a system and method for testing one or more semiconductor devices (e.g. packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures is determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable. The semiconductor device may be binned differently depending on the number of identified failures. The decision circuitry may designate the semiconductor device for an additional procedure, if the number of the identified failures is within a first number set. The decision circuitry may designate the semiconductor device for repair, if the number of the identified failures is within a second number set.

Abstract: A lifting mechanism for a sedimentation tank is provided for vertically raising and lowering a rake assembly in such sedimentation tank. The lifting mechanism comprises one or more elongate members pivotally connected to certain structural elements of the assemblage, such as the rotary drive motor, rake assembly, column or bridge. The pivotal connections of the elongate members are positioned about a horizontal axis and are oriented to receive the torque forces imposed on the assemblage as the rake assembly rotates in the tank simultaneously with vertical lifting. The torque forces are translated into the pivotal connections and are able to counteract those forces to facilitate vertically raising and lowering the rake assembly while it is being rotated in the sedimentation tank.

Abstract: A high density vertical surface mount package and thermal carrier therefor including a heat sink.

Abstract: An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary die temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.

Abstract: An electrochemical reaction assembly and methods of inducing electrochemical reactions, such as for deposition of materials on semiconductor substrates. The assembly and method achieve a highly uniform thickness and composition of deposition material or uniform etching or polishing on the semiconductor substrates by retaining the semiconductor substrates on a moving cathode immersed in an appropriate reaction solution wherein a wire mesh anode rotates about the moving cathode during electrochemical reaction.

Abstract: The invention disclosed herein is a semiconductor die assembly and method of making the same having a die and insert substrate that are electrically interconnected by diffusing gold bumps attached to the connecting surface of the substrate to aluminum-based bond pads on the die to form a permanent die-to-insert connection. The process for diffusing the gold bumps into the bond pads preferably occurs during a burn-in process wherein pressure and heat are applied to the die/substrate assembly without melting the gold bumps until a permanent die-to-insert substrate connection is properly made.

Abstract: Devices and methods for reducing lead inductance in integrated circuit (IC) packages. More specifically to an integrated circuit package configuration for high speed applications where the inductance of the leads is reduced or minimized in high capacity semiconductor device packages. The integrated circuit package assembly comprises a substrate, semiconductor device, insulating covering or coating, if desire, a semiconductor device retainer, lead frame, and wire bond interconnections.

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality of lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both plurality of lead finger of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.

Abstract: Implantation of germanium (45) into a PMOS buried channel to permits the enhancement implant profile (to 45) to be made more shallow. The shallow profile will reduce or eventually solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep submicron range. Benefits include better short channel characteristics, i.e., higher punch through voltage BVDSS, less VT sensitivity to the drain voltage (defined as curl) and better subthreshold leakage characteristics.