Abstract: Techniques are provided for automatically deploying software packages. Management agents represent these packages, a logical tree represents the deployed structure, and a node of the tree represents a management agent. A node that does not have any child node is referred to as a leaf node. A recursive process associated with at least one repository generates the structure. The repositories include information for configuring the nodes and thus control the deployment process. During deployment, a non-leaf node, referred to as an initiator node, uses information received from a corresponding repository to generate its child nodes. A child node, if being an initiator node, recursively generates its child nodes until the recursive process stops as there is no additional child node to be generated. Further, node identifiers are automatically established and assigned to respective nodes.

Abstract: Techniques for storing data used in making announcements in telephone communications are disclosed. In an embodiment, an announcement depends on classes of services associated with telephone subscribers. The classes of services represent call types or call features such as call-forwarding unconditional, call-forwarding busy, call-forwarding no answer, etc. A first database associates subscribed phone numbers with a class of service. A second database defines the class of services such as the call types, the telephone digit pattern in the subscribed telephone numbers, the condition for an announcement, etc. A third database defines a default class of service for use in case a phone number is not associated with a class of service in the first database.

Abstract: The present invention, in various embodiments, provides techniques for managing memory in computer systems. One embodiment uses a memory table having entries to locate data residing in different types of storage areas, such as physical memory, hard disc, file servers, storage devices, etc. Upon a program accessing memory for a particular piece of data, the memory table translates the data's physical address to an address used to find the table entry pointing to the requested data. In one embodiment, if the data is in physical memory, then the requested data is returned to the program. However, if the data is not in physical memory and it is determined that the data will be used frequently, then the data, in addition to being returned, is also brought to the physical memory for later use. This is because accessing the data from physical memory usually takes less time than accessing the data from other storage devices.

Abstract: Techniques are provided for recovering from compilation errors in environments that use dynamic compilers. Application programs include Java bytecodes, and compilation includes sequential invocation of separate compilation phases on a region of bytecodes. If compilation of a region results in a fatal error, then the compiler identifies the “failed” phase. If the failed phase is a non-essential phase, then the compiler attempts to re-compile the region after skipping the failed phase. However, if the failed phase is essential, then the compiler attempts to replace that failed phase with a simpler version. Nevertheless, if the fatal error cannot be avoided or the compiler is unable to replace the failed phase with a simpler version, then the compiler prevents compilation of the code encompassing the fatal error in future attempts.

Abstract: A circuit that allows selection of a power source among a plurality of power sources is disclosed. In an embodiment, either one or both voltage sources Vaux and Vapp may be available in a system. If both sources are available, then the circuit enables the system to use source Vaux. However, if only one of the two sources is available, then the circuit enables the system to use that available source.

Abstract: The present invention, in various embodiments, provides techniques for allocating resources for efficient use by a program. In one embodiment, a method implementing the techniques comprises the steps of identifying an I/O device connected to a storage device storing data associated with the program, and allocating memory arrays and a processor both of which having a shortest distance to the I/O device. In one embodiment, the resources reside in a plurality of nodes each of which includes one or a combination one or more of an I/O device, memory arrays, and a processor. Further, the resources are grouped in a node if they are on the same system bus or if they are connected to a chip providing point-to-point links to resources. In one embodiment, the relative distance between the resources is stored in a table embedded in firmware portable from one operating system to another operating system.

Abstract: The present invention, in various embodiments, provides techniques for managing system power. In one embodiment, system compute loads and/or system resources invoked by services running on the system consume power. To better manage power consumption, the spare capacity of a system resource is periodically measured, and if this spare capacity is outside a predefined range, then the resource operation is adjusted, e.g., the CPU speed is increased or decreased, so that the spare capacity is within the range. Further, the spare capacity is kept as close to zero as practical, and this spare capacity is determined based on the statistical distribution of a number of utilization values of the resources, which is also taken periodically. The spare capacity is also calculated based on considerations of the probability that the system resources are saturated.

Abstract: Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other processing cell. A processing cell may include a program counter, an instruction memory, and appropriate elements such as a branch lookup, a branch unit, etc. Alternatively, the processing cell may include a state machine that replaces the program counter and the instruction memory. Embodiments of the invention are able to support the VLIW mode, the MIMD) mode, a mixture of both modes of execution, etc.

Abstract: The present invention, in various embodiments, provides techniques for retiring instructions that typically complete early as compared to most instructions. In a first embodiment, at each stage of the various processing stages, each instruction capable of early retirement is processed in accordance with that stage. At a particular stage, if the instruction meets the criteria for early retirement, then the instruction is terminated, e.g., “retired,” and the system is updated to reflect that the instruction has been terminated. However, if, at that particular stage, the instruction does not meet the criteria for early retirement, then the instruction is processed to the next stage, and it is determined again whether the instruction meets the criteria for early retirement. If the instruction meets the criteria, then the instruction is terminated, or if the instruction does not meet the criteria, then the instruction is processed to the next stage, and so on, until the instruction is retired.

Abstract: The present invention, in various embodiments, provides techniques for testing devices. In one embodiment, the device under test is a chip including a plurality of processors and a memory structure that stores test programs. One or more processors executes the test programs and generates test results based on which the chip may be determined good or bad. In one embodiment, the processors execute the test programs independent of each other, and no external hardware and/or test controller is required during the test phase. Various embodiments include a first processor that controls the scan chain of a second processor; the test results of the first processor are used as inputs for testing the second processor, etc.

Abstract: Techniques are disclosed for hot-swapping devices in a computer system while maintaining the system integrity. One embodiment of the techniques uses an interface bridge between the system and a device complying with the Integrated Drive Electronic (IDE) standard. The bridge uses the IDE protocol to communicate with the device and uses the Small Computer System Interface (SCSI) protocol to communicate with the system. Consequently, with respect to the system, the bridge is treated as a SCSI device. In accordance with the techniques disclosed herein, hot swapping the device occurs on one side of the bridge, and the system on the other side of the bridge is well informed of such hot swapping in order to respond accordingly. As a result, the bus on the system side, is shielded from hot swapping disruption, thereby maintaining the system integrity.

Abstract: The present invention, in various embodiments, is directed to techniques for providing debugging capability for program code instrumentation. In one embodiment, an instrumentor inserts an instrumentation breakpoint at the beginning of a block of original code. When this breakpoint is reached during execution of the application program that includes the block of original code, the instrumenator, from the block of original code, generates a block of instrumented code. This block of instrumented code may include debugging breakpoints that are carried from the block of original code or are inserted into the block of instrumented code during debugging. After generating the instrumented code, the instrumentor executes the instrumented code until debugging breakpoints are reached that stop the program flow, thereby allowing a programmer to perform debugging functions at these debugging breakpoints.

Abstract: The present invention provides techniques for retiring instructions that typically complete early as compared to most instructions. In an embodiment, instructions capable of early retirement are processed in accordance with the various processing stages. At a particular stage, if an instruction meets the criteria for early retirement, then that instruction is terminated, e.g., “retired,” and the system is updated to reflect that the instruction has been terminated. However, if the instruction does not meet the criteria for early retirement, then the instruction is processed to the next stage, and it is determined again whether the instruction meets the criteria for early retirement. If the instruction meets the criteria, then the instruction is terminated, or if the instruction does not meet the criteria, then the instruction is processed to the next stage, and so on, until the instruction is retired.

Abstract: The present invention, in various embodiments, provides techniques for managing latencies in accessing memory of computer systems. In one embodiment, upon accessing the memory system for a piece of data used by a first process, a latency manager determines the access time to acquire the piece of data in the memory system. The latency manager then compares the determined access time to a threshold. If the determined access time is greater than the threshold, the latency manager triggers an interrupt for the operating system to switch threads or processes so that execution of the first process is postponed and execution of a second process starts. Various embodiments include the latency manager is polled for the access time when the processor is stalled, the latency manager triggers a process switch when a particular memory subsystem is accessed, etc.

Abstract: Techniques are provided for retiring instructions that typically complete early as compared to most instructions. In an embodiment, all instructions are processed normally until the instruction queue is full. At that time, the system is frozen, e.g., all units stop processing instructions. For each instruction in the instruction queue, if the instruction meets the criteria for early retirement, then the instruction is terminated and the system is updated to reflect that the instruction has been terminated. The system is then unfrozen, and all units resume their functions.

Abstract: Techniques are disclosed for preserving first content in a first register. In one embodiment, the first register is a general register, a second register is a UNaT register, and each general register is associated with a NaT bit. To preserve the content of the UNaT register while saving the content of a general register and its associated NaT bit, the content of the general register is saved to a floating-point register, and the NaT bit associated with the general register is also saved. If the NaT bit is set, then only the NaT bit is restored. Conversely, if the NaT bit is not set, then both the content of the general register and the NaT bit are restored.

Abstract: The present invention, in various embodiments, provides techniques for managing memory in computer systems. In one embodiment, each memory page is divided into relocation blocks located at various physical locations, and a relocation table is created with entries used to locate these blocks. To access memory for a particular piece of data, a program first uses a virtual address of the data, which, through a translation look-aside buffer, is translated into a physical address within the computer system. Using the relocation table, the physical address is then translated to a relocation address that identifies the relocation block containing the requested data. From the identified relocation block, the data is returned to the program.

Abstract: The present invention, in various embodiments, provides techniques for managing data in a queue. In one embodiment, two write pointers control writing into a memory queue and one read pointer control reading from the queue. Individual entries written into the queue may complete out-of-order and depend on various conditions such as whether the pointer associated with the entries is active or passive, whether the other pointer is tracking a transaction, whether the active pointer is lower, equal to, or higher than the inactive pointer, whether the data is the last piece of data in a transaction, etc. Data read from the queue is in the order of the transaction headers written into the queue. The data may bypass the queue, i.e., the data is not written into the queue, but is loaded directly to an output register.

Abstract: Techniques are disclosed for hot-swapping devices in a computer system while maintaining the system integrity. One embodiment of the techniques uses an interface bridge between the system and a device complying with the Integrated Drive Electronic (IDE) standard. The bridge uses the IDE protocol to communicate with the device and uses the Small Computer System Interface (SCSI) protocol to communicate with the system. Consequently, with respect to the system, the bridge is treated as a SCSI device. In accordance with the techniques disclosed herein, hot swapping the device occurs on one side of the bridge, and the system on the other side of the bridge is well informed of such hot swapping in order to respond accordingly. As a result, the bus on the system side, is shielded from hot swapping disruption, thereby maintaining the system integrity.

Abstract: The present invention, in various embodiments, provides techniques for reducing effects of electrical impedance. In one embodiment, the impedance is in the form of inductance and arises from vias in a termination PCB and from resistors used on the PCB. In one embodiment, a power plane is placed near the resistors. Additional power and ground planes are created in parallel among themselves and perpendicular to the vias, which cause capacitance to be formed between each pair of the ground and power planes, the ground planes and the vias, and the power planes and the vias. In one aspect, the power plane near the resistors and the formed capacitance allow the high-frequency returned currents to flow through a smaller loop and thus be affected by a smaller inductance. Additionally, the created capacitance reduces both the total impedance of the vias and the resistors and any impedance that result from power-ground discontinuity.