Abstract: An electronic digital crossconnect system electronically interconnecting individual subscriber channels between various higher rate digital facilities. The system provides for a simplified, lower-speed information bus structure, improved reliability, and the ability to connect intact a high rate digital facility without super frame alignment.

Abstract: An interface circuit interfaces a four wire telephone circuit to a telephone headset. An adjustable receiver portion of the interface circuit receives a line input signal from the four wire circuit and produces a headset input signal limited to a predetermined signal level. An adjustable output portion of the interface circuit accepts a headset output signal and conditions it for use as a line output signal on the four wire circuit. A DC voltage is also supplied to a headset microphone through the output portion of the interface circuit.

Abstract: An alignment circuit for use in a synchronous data transfer system for logically comparing the phase of a returned clock signal having an unknown phase relative to a local clock such that the local clock or its inverse can be used to retime returned remote data without the possibility of generating errors due to the lack of set-up time and hold time requirements for actuating a D flip-flop gate at its clock input with respect to the data arriving a the D input of the D flip-flop. The phase of the local clock relative to the return clock is detected and compared with a threshold phase shift value. If the phase shift is negligible, the remote data is clocked by the inverted local clock. If the phase shift exceeds the threshold value, the remote data is clocked by the local clock.

Abstract: The present invention uses a plurality of spaced contact fingers to provide EMI (electromagnetic interference) shielding at the gap junction between the edge of a sheet metal panel and its butt interface with a narrow flat surface. Each of the fingers comprises a U-shaped portion enclosing the sheet metal panel edge and a V-shaped portion situated substantially at right angles to the U-shaped portion and urging the U-shaped portion in an outwardly direction so as to provide contact between the sheet metal panel and the flat surface to which it is interfacing.

Abstract: A very wide bandwidth, wide dynamic range amplifier incorporating a plurality of feedback paths which are parallel connected upon command is illustrated. The parallel connection is actuated from an input signal strength sensor which has built-in hysteresis so that there is no continuous switching from one feedback configuration to the other at a given input signal strength. The design of the switch feedback path is such that there is very low capacitance at the input of the amplifier, and a single signal peaking compensation circuit can be used to prevent undesirable signal peaking in the response curve.

Abstract: The present invention relates to a checking circuit concept which determines the integrity of data passing through a further circuit to be checked such as an elastic buffer. The concept is based on the fact that a serial data stream entering an elastic buffer must exit the elastic buffer intact without bit errors. Since the bit delay through the elastic buffer is a variable, it becomes difficult to test bit integrity. The present invention determines the bit integrity by sampling and storing a sequential set of data entering the elastic buffer and successively comparing it to data exiting the buffer. If no errors are present, the stored input data will match the data exiting the elastic buffer within N bits where N equals the storage bit location size of the elastic buffer.

Abstract: An analog echo suppression circuit is used with a telephony 2-wire circuit to 4-wire circuit interface. The 2-wire circuit carries a first signal and the 4-wire circuit carries a second signal. Each circuit has an input port and an output port. The interface produces an echo signal on the output of the 2-wire circuit when the second signal is received at the input port of the 2-wire circuit. A first communication channel connects the output of the 4-wire circuit to the input of the 2-wire circuit. A second communication channel connects the output of the 2-wire circuit to the input of the 4-wire circuit and series analog switches or transmission gates can interrupt the second channel. A comparator circuit receives the first and second signals from the first and second channels and has first and second outputs.

Abstract: The realization that field effect transistor current can be controlled by adjusting the gate voltage and thereby controlling the amplifier power consumption with only a slight degradation of RF gain and signal quality is utilized in a hot standby radio system configuration. The standby amplifier is left in an ON condition with the gate voltage adjusted to a low value until such time as the amplifier is needed for active service. At this time the gate voltage is adjusted to the optimal value and the amplifier is operated in a normal condition. The standby mode still allows tests to ascertain whether or not the amplifier is operational while conserving substantial amounts of power.

Abstract: A constant resistance loss/slope filter circuit has a plurality of cascaded circuit sections. Each circuit section has a fixed resistive pad and a slope equalizer. Each circuit section also has a switch for switching inputs and outputs of the circuit sections between the fixed resistive pad and the slope equalizer. Each of the circuit sections has a fixed resistive pad with a different predetermined value loss and a slope equalizer with a different predetermined value of a slope.

Abstract: A circuit using the non-linear charge characteristics of a RC network to, in combination with a consecutive bit logic detector circuit, establish a given integrated output if the consecutive bit check indicates noncorrelation anymore often than once per framing bit. This is accomplished by having the discharge rate for correlation greatly exceed the amount of charge for noncorrelation at the amplitude levels against which the signal is checked relative a reference for determining whether or not in fact an alarm indication signal does exist.

Abstract: A controllable switch matrix module is disclosed for bidirectional transmission of signals between multiple ports in a single module, where the attenuation characteristics are dynamically alterable. The invention uses pin diodes both for isolation and for switching, and achieves its high isolation in part by completely enclosing each of the attenuation functions within separate compartments, enclosing the connections between compartments for isolation between functions, and supplying control signals to the pin diodes using feedthrough connections designed in such a way as to prevent the emission of RF signals via the feedthrough devices. Only two bits are required to define any one of four attenuation levels between any two ports.

Abstract: A logic circuit for detecting when the sign and most significant error bit of the digital values defining the data vector for either the In-phase or quadrature-phase have identical logic values. As illustrated, a pair of counters is used to provide an integrator with one of the counters receiving all error indications and the other receiving "good" indications and an output is provided when one of the counters first reaches a full count condition. Thus, the integrator provides an out-of-lock condition when there is an error indicative condition for more than half of a predetermined number of counts.

Abstract: A data scrambler-descrambler combination is illustrated which stores previously modified received data and alters data passing through on the basis of certain of the previously stored data bits. Additionally, the previously stored data is monitored to detect repetitive patterns, which indicate that the scrambler is no longer properly scrambling the signal, and introducing a pattern breaking data bit into the storage means whenever such a pattern is detected.

Abstract: An embedded circuit is placed in a phase-locked loop having the normal phase detector and voltage-controlled oscillator. The embedded circuit is transparent to phase-locked conditions of the loop and becomes operative in an oscillatory mode only when the loop loses its lock. An oscillatory detector is used to detect the oscillatory condition of the embedded circuit and causes the application of a sweep signal to the voltage-controlled oscillator to reestablish phase-locked conditions in the overall phase-locked apparatus.

Abstract: A phase-lock loop system incorporates a normally "transparent" oscillator used in detecting whether or not the system is in a locked condition. It is essential that the oscillator, a portion of which is serially involved in the phase-lock loop, have a long time constant, so as to minimally affect the closed loop's transfer function during phase-locked conditions. It is desirable, however, that when the phase-lock loop loses lock that the time constants of the transparent oscillator change to much smaller values for quick response of the oscillator and operation at a high frequency for detection purposes and quick extinction when phase-lock is acquired. The detection of oscillation of the transparent oscillator initiates the application of a low speed sweep signal being applied to the voltage controlled oscillator portion of the phase-lock loop to reestablish phase-locked conditions and eventually return of the transparent oscillator to its long time constant values.

Abstract: An autoequalizer having first and second data stores, first and second coefficient stores along with first and second multipliers for multiplying each stored data sample times its corresponding stored coefficient is disclosed. First and second accumulators accumulate the results of the first and second multipliers for an entire window of consecutive data samples. The results from the first and second accumulators are summed with feedback before being tested against various threshold values. In a preferred arrangement, for use with dual information channels, mirror image equalizer elements are connected in a feedback arrangement with each other.

Abstract: A system is illustrated for making sure that received data and the master clock are in the proper relationship even though temperature, voltage supplies and aging cause variable transmission time delays between the source of data and the local circuit. This proper relationship is accomplished by detecting the phase difference between a local master oscillator and the received data and providing a clock signal to be used by the remote data sending device in a system phase-locked loop using a slave oscillator and the previously mentioned phase detection circuit. The slave oscillator tracks the frequency of the master oscillator and the phase of the incoming data. Since a clock signal was previously required for prior art systems, this approach eliminates the return clock that was required if the cable length and the associated data signal delay parameters could vary.

Abstract: The present inventive concept combines two signals, each representative of a portion of a single signal, wherein the two signals have different non-linear slopes, and produces a single linearly changing output signal indicative of the combination. This circuit is specifically used in combination with the feedback loop of a delayed automatic gain control circuit to detect the signal level applied to the gain control circuit and to provide a linearly changing output signal representative of the decibel value of the signal applied to the automatic gain control circuit. This is accomplished by linearizing the two different signals independently, and establishing a maximum value for one signal, a minimum value for the other signal, and summing these in conjunction with a reference to produce a single composite linearly changing signal.

Abstract: An all digital equivalent to a voltage controlled oscillator with low intrinsic jitter and the absence of sample aliasing within a nonzero bandwidth, the offset (non-symmetrical) digitally controlled oscillator comprising a divider (divide by n or n-1) which is timed from a high speed reference clock, a 2.sup.m counter and a digital comparator. The divider divides the high speed reference clock signal so that for every thirty second cycle of the high speed reference clock a pulse is output from the present invention. The output pulse is input to the 2.sup.m counter and increments same. The 2.sup.m counter counts the number of output cycles (or pulses) that have occurred since the last phase adjustment and comares this m-bit number to the input to the present invention. When the output of the 2.sup.m counter becomes greater than or equal to the input, a divide by n-1 signal is sent to the divider which shortens the output cycle and adjusts the average output frequency and phase. The 2.sup.

Abstract: Phase quantizer apparatus in an all digital phase locked loop to provide a two-part digital number representing the phase of the input signal (a noncontinuous pulse train) relative to the output signal of the all digital phase locked loop. The phase quantizer comprises a write counter (modulo m counter) and a phase counter (modulo n counter) which receive the noncontinuous pulse train as an input signal. The leading pulse edge in the noncontinuous pulse train increments the write counter and resets the phase counter. The write counter comprises a binary counter and a conversion circuit. The binary counter portion of the write counter was being used and is still being used in the digital communications system to provide address information to the elastic buffer to read data into predetermined storage locations in the elastic buffer.