Patents Represented by Attorney Victor F. Lohmann, III
  • Patent number: 5144671
    Abstract: A method of encoding speech includes a limited search of a tree-code excitation codebook with a closed loop gain calculation for each test path under consideration. The gain calculation occurs when minimizing an error distance measurement between a synthetic signal defined by each test path being considered and the appropriate speech signal by optimizing a scaling factor of the synthetic signal. The encoding method achieves a significant reduction in computational complexity with minimal loss of performance.
    Type: Grant
    Filed: March 15, 1990
    Date of Patent: September 1, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Baruch Mazor, Dale E. Veeneman
  • Patent number: 5144206
    Abstract: The present invention describes an electrodeless HID lamp fixture which utilizes conventional microwave printed circuit material to provide both coupling and impedance matching functions. The fixture provides a steady state input impedance of a predetermined (e.g. 50 .OMEGA. or 75 .OMEGA.) value allowing direct connection to a RF power supply. Microwave power is applied at the input of the impedance matching network/balun which transforms the steady-state impedance of the lamp to the predetermined value. The network include a quarter wave transformer having a shunt capacitor coupled to balun-applicator which supplies microwave power to the lamp. In a preferred embodiment, the quarter wave transformer, shunt capacitor and balun are all manufactured on a microstrip.
    Type: Grant
    Filed: September 10, 1991
    Date of Patent: September 1, 1992
    Assignee: GTE Products Corporation
    Inventors: Scott J. Butler, Walter P. Lapatovich, Jason Bochinski
  • Patent number: 5130612
    Abstract: A high frequency applicator for energizing electrodeless lamps is described. The applicators are made of two loops of wire electrically attached to the ends of phased feed points of a planar transmission line. The loops are face each other and are positioned so as to form a gap in which a lamp capsule is placed. Each loop is made of three partial turns, the first and second turns being parallel to each other, each partial turn having a first and second end and the third partial turn is attached to the second end of each partial turn and positioned orthogonal the first and second turns. The plane formed by the third turn makes a dihedral angle between 9.degree. and 135.degree. with the planar transmission line.
    Type: Grant
    Filed: September 11, 1991
    Date of Patent: July 14, 1992
    Assignee: GTE Products Corporation
    Inventors: Walter P. Lapatovich, Scott J. Butler, Jason R. Bochinski
  • Patent number: 5126805
    Abstract: A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to form a germanium-silicon composite. A rapid thermal anneal is performed to recrystallize the germanium-silicon composite. Alternatively, a single crystal epitaxial layer may be deposited on the silicon. Conventional metallization procedures are employed to produce ohmic source and gate contact members to the germanium-silicon composite or the epitaxial germanium of the source and gate regions. By virtue of the reduced bandgap provided by the presence of the germanium, the contact resistance of the device is reduced.
    Type: Grant
    Filed: October 5, 1990
    Date of Patent: June 30, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Emel S. Bulat, Marvin J. Tabasky
  • Patent number: 5121457
    Abstract: A method for coupling light from one or more light-emitting devices into corresponding optical fibers includes placing the light-emitting devices on the top surface of a substrate and forming, by photolithographical means, on the top surface of said substrate V-grooves for holding fibers in precise relationship with said light-emitting devices. Additionally, alignment pedestals or posts are formed on said substrate in predetermined relationship to the light emitting devices and alignment V-grooves are photolithographically formed on the top surface of said substrate parallel to said fiber V-grooves. The substrate is cleaved into two sections and said sections are assembled in orthogonal relationship with the section containing the light-emitting devices and alignment posts section being secured to the section containing the fiber and alignment V-grooves so that said posts fit into said alignment V-grooves, thereby aligning the fiber V-grooves with the light-emitting devices.
    Type: Grant
    Filed: May 21, 1991
    Date of Patent: June 9, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Barbara M. Foley, Paul Melman, W. John Carlsen
  • Patent number: 5119392
    Abstract: A second-order predistortion circuit for linearizing a nonlinear device having a transfer function of the form F=C.sub.1 I.sub.1 -C.sub.2 (I.sub.1).sup.2, where I.sub.1 is a current applied to an input of the nonlinear device, and C.sub.1 and C.sub.2 are constants. The nonlinear device is typically a laser diode. The predistortion circuit includes a field effect transistor biased for square law operation. An input voltage is applied between the gate and source electrodes of the field effect transistor. An amplifier is connected between the drain electrode of the field effect transistor and the input of the nonlinear device. The gain of the amplifier is selected to minimize second-order distortion in the output of the nonlinear device as a function of the input voltage to the field effect transistor.
    Type: Grant
    Filed: November 21, 1990
    Date of Patent: June 2, 1992
    Assignee: GTE Laboratories Incorporated
    Inventor: Richard B. Childs
  • Patent number: 5111254
    Abstract: A junction field effect transistor having an array of electrically floating gate elements located between the control gate and the drain in the path of current flow from the source to the drain. As the drain voltage increases the depletion zone of the control gate expands until it reaches the nearest floating gate. The maximum electric field at the control gate is clamped while the nearest floating gate increases in potential and its depletion zone expands toward the next floating gate, and so on. In this way the applied voltage is spread over the array of floating gates clamping the maximum electric field at a value that is less than the avalanche breakdown field. Then, the avalanche breakdown voltage of the device is increased.
    Type: Grant
    Filed: August 17, 1990
    Date of Patent: May 5, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Mark Levinson, Brian M. Ditchek, Philip G. Rossoni, Frederick Rock
  • Patent number: 5106770
    Abstract: In the fabrication of a junction field effect transistor, specifically a static induction transistor, an epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity N-type silicon. A plurality of elongated parallel grooves separated by interposed ridges are formed by reactive ion etching. A layer of silicon oxide is grown on all exposed surfaces including the side walls and bottoms of the grooves. Fluorine is ion implanted into the silicon oxide. The grooves are filled with deposited silicon oxide or polycrystalline silicon, and material is removed to form a flat planar surface with the silicon at the surfaces of the ridges exposed. P-type doping material is ion implanted into alternate (gate) ridges. The wafer is heated to diffuse the P-type doping material and form gate regions. Heating also activates the implanted fluorine ions which react with unbonded silicon atoms at the silicon oxide-silicon interface thus quenching vacant bond sites.
    Type: Grant
    Filed: November 16, 1990
    Date of Patent: April 21, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Emel S. Bulat, Richard M. Klein
  • Patent number: 5103455
    Abstract: An optical preamplifier includes a semiconductor optical amplifier monolithically integrated with an optical detector and electrically isolated from the detector by an isolation region. The isolation region consists of a low-loss, preferably transparent, insulating material whose index of refraction is matched to at least the refractive index of the amplifier, leading to reduced facet reflectivity at the amplifier output facet. Alternative device structures may include a waveguiding layer in the isolation region, a grating integrated with or following the optical amplifier, and a tuning region positioned between the amplifier and isolation region for filtering spontaneous emission.
    Type: Grant
    Filed: May 9, 1990
    Date of Patent: April 7, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Elliot Eichen, Roger P. Holmstrom, Joanne LaCourse, Robert B. Lauer, William Powazinik, William C. Rideout, John Schlafer
  • Patent number: 5098862
    Abstract: Electrical ohmic contacts are made to a matrix of silicon having conductive rods embedded therein without making contact to any of the rods. Those rods which extend to the surface in the selected area of the matrix to be contacted are etched to form holes. The holes are filled with insulating polycrystalline silicon. The region of the selected area is heavily doped, and an ohmic contact member is made thereto. The underlying rods are spaced from the ohmic contact member and the heavily-doped region by intervening polycrystalline silicon.
    Type: Grant
    Filed: November 7, 1990
    Date of Patent: March 24, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Brian M. Ditchek, Marvin Tabasky
  • Patent number: 5093225
    Abstract: A semiconductor mesa structure is covered with a photoresist material in a localized flooding manner such that the photoresist material is thinner on the top of the mesas and also at the upper most portion of the sidewalls than at the base of the mesa and the intervening channel. The photoresist is then exposed through a mask in a manner so that when developed, the photoresist from the mesa top and upper most portion of the sidewall can be removed. When the photoresist is exposed to the actinic radiaction, the thinner photoresist is adequately exposed more rapidly than the thicker portion nearer the bottom of the mesa, if the mask does not adequately shield the actinic radiation from reaching it. Thus the alignment tolerance is greater than if the photoresist were of uniform thickness.
    Type: Grant
    Filed: September 14, 1990
    Date of Patent: March 3, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Roger P. Holmstrom, Edmund Meland, F. David Crawford
  • Patent number: 5082799
    Abstract: A semiconductor laser having a high modulation bandwidth is made by utilizing an InGaAsP cap layer and an InGaAsP active layer of different crystal structure. Channels are anisotropically etched through the cap, cladding and active layers and partially through the buffer layer. The active and cap layers a laterally etched and a semi-insulating material is overlaid the sidewalls. A further etching leaves a thin wall of the semi-insulating material surrounding the active layer. 1.3 .mu.m InGaAsP lasers with 3 dB bandwidths of 24 GHz and intrinsic resonance frequencies in excess of 22 GHz have been successfully fabricated. This is the highest bandwidth ever reported for a semiconductor laser, and the highest resonance frequency for InGaAsP lasers. Excellent modulation efficiencies are observed to high frequencies.
    Type: Grant
    Filed: September 14, 1990
    Date of Patent: January 21, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Roger P. Holmstrom, Edmund Meland, William Powazinik
  • Patent number: 5079616
    Abstract: Heteroepitaxial semiconductor structures of, for example, GaAs on InP or Si. The epitaxially grown GaAs is in the form of individual spaced-apart islands having maximum dimensions in the plane of the surface of the substrate of no greater than 10 micrometers. In islands of this size stress in the plane of the epitaxially grown layers due to mismatch of the coefficients of thermal expansion of the substrate and epitaxially grown materials is insignificant.
    Type: Grant
    Filed: February 11, 1988
    Date of Patent: January 7, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Ben G. Yacobi, Stanley Zemon, Chirravuri Jagannath
  • Patent number: 5077878
    Abstract: A method of passively aligning optical receiving elements such as fibers to the active elements of a light generating chip includes the steps of forming two front and one side pedestal structures on the surface of a substrate body, defining a vertical sidewall of the chip to form a mating channel having an edge at a predetermined distance from the first active element, mounting the chip epi-side down on the substrate surface, and positioning the fibers in fiber-receiving channels to that a center line of each fiber is aligned to a center line of a respective active element. When mounted, the front face of the chip is abutting the contact surfaces of the two front pedestals, and the defined sidewall of the mating channel is abutting the contact surface of the side pedestal. The passive alignment procedure is also effective in aligning a single fiber to a single active element.
    Type: Grant
    Filed: July 11, 1990
    Date of Patent: January 7, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Craig A. Armiento, Chirravuri Jagannath, Marvin J. Tabasky, Thomas W. Fitzgerald, Harry F. Lockwood, Paul O. Haugsjaa, Mark A. Rothman, Vincent J. Barry, Margaret B. Stern
  • Patent number: 5069561
    Abstract: A monolithically integrated optical preamplifier comprises an amplifying region, an optical detection region for detecting amplified light, and an optically transparent and electrically insulating isolation region interposed between the amplifying and optical detection regions. The amplifying region achieves reduced facet reflectivity by being designed to have a large spot size, single-traverse mode waveguide amplifier oriented at an angle with respect to a crystal plane through the preamplifier. The isolation region is preferably an air gap.
    Type: Grant
    Filed: July 24, 1990
    Date of Patent: December 3, 1991
    Assignee: GTE Laboratories Incorporated
    Inventors: William C. Rideout, Roger P. Holmstrom, Elliot Eichen, William Powazinik, Joanne LaCourse, John Schlafer, Robert B. Lauer
  • Patent number: 5068723
    Abstract: An adaptive vector quantization scheme suitable for packet video adapts to the varying characteristics of the actual images sequence being compressed. A large code book is divided into two sections, having higher and lower priority, representing common characteristics and specific characteristics of images. Each new image to be coded is first compared to the common characteristics section of the code book. If a match of acceptable quality is not found, then it is compared to the specific characteristics section. The best match of the two sections is utilized. Entries in the two sections are reorganized and/or exchanged as a function of the usage of the code vectors therein. The rate and extent of adaptation is dictated by the update interval and the desired level of quality, respectively, without requiring any transmission of the vectors themselves or the side information.
    Type: Grant
    Filed: July 24, 1990
    Date of Patent: November 26, 1991
    Assignee: GTE Laboratories Incorporated
    Inventors: Sudhir S. Dixit, Yushu Feng
  • Patent number: 5066603
    Abstract: In fabricating a junction field effect transistor, specifically a static induction transistor, an epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is marked in a pattern to expose a plurality of elongated surface areas. The wafer is subjected to reactive ion etchings in SiCl.sub.4 and Cl.sub.2 and subsequently in Cl.sub.2 to form parallel grooves with rounded intersection between the wide walls and bottoms of the grooves. Ridges of silicon are interposed between grooves. A layer of silicon oxide is grown on all the silicon surfaces. The grooves are filled with deposited silicon oxide and silicon oxide is removed to form a planar surface with the upper surfaces of the ridges.
    Type: Grant
    Filed: September 6, 1989
    Date of Patent: November 19, 1991
    Assignee: GTE Laboratories Incorporated
    Inventors: Emel S. Bulat, Brian T. Devlin
  • Patent number: 5060285
    Abstract: A vector quantization based image compression technique which exploits inter-block correlation and layered addressing structure to form variable block sizes. Without introducing any quality degradation, when compared to the traditional vector quantization algorithms, the invention described herein significantly increases the compression and reduces the bit rate. The concept of inter-block correlation is utilized to form variable size blocks, which are then coded using a hierarchical coding model. The method is based on starting off from a small basic block which is allowed to grow to a maximum of a preset block size as long as certain conditions are met. The basic idea of growing the block is based on the renormalization group theory in physics. The algorithm utilizes only one pixel code book for the basic block size and several address code books for the layer block sizes to encode an image. S/N ratio in excess of 30 dB at bit rates lower than 0.2 bpp are easily obtained.
    Type: Grant
    Filed: May 19, 1989
    Date of Patent: October 22, 1991
    Assignee: GTE Laboratories Incorporated
    Inventors: Sudhir S. Dixit, Yushu Feng
  • Patent number: 5058060
    Abstract: An optical memory cell constructed from an optical combiner, a 1.times.2 optical swtich and optical fibers. One input port of the optical combiner serves as the input to the memory cell. The output port of the optical combiner is connected to the input of the optical switch by an optical fiber. A first output port of said switch is connected by an optical fiber to the second input of the optical combiner, such that when said switch is in the straight-through state, an optical loop is formed through which an optical pulse can circulate. The second output of the optical switch serves as the output of the memory cell when said optical switch is in the cross-over state. Control signals are provided by a clock.
    Type: Grant
    Filed: April 19, 1990
    Date of Patent: October 15, 1991
    Assignee: GTE Laboratories Incorporated
    Inventor: Shing-Fong Su
  • Patent number: 5053843
    Abstract: An IMSM photodetector structure comprises a GaAs substrate, a buffer region grown on the substrate, an optically active absorbing layer of In.sub.0.42 Ga.sub.0.58 As grown on the absorbing layer. The buffer region includes in sequence a first layer of In.sub.0.23 Ga.sub.0.77 As, an In.sub.0.46 Ga.sub.0.54 As/GaAs superlattice, and a second layer of In.sub.0.23 Ga.sub.0.77 As. An interdigitated pattern of Schottky metal contacts is fabricated on the Al.sub.0.3 Ga.sub.0.7 As/GaAs superlattice. This structure is useful in fabricating long-wavelength, monolithic receivers based on GaAs MESFET technology since the optical and electrical characteristics of the structure are preserved during the thermal annealing cycle necesary in ion-implaned GaAs MESFET processes.
    Type: Grant
    Filed: December 12, 1990
    Date of Patent: October 1, 1991
    Assignee: GTE Laboratories Incorporated
    Inventors: A. N. M. Masum Choudhury, Chirravuri Jagannath, Boris S. Elman, Craig A. Armiento