Abstract: A computer system including a memory controller programmed with associated burst order translation logic and coupled to one or more microprocessors and including a memory circuit which supports either sequential or interleaved transmission of burst data communication between an I/O devices and one or more of the microprocessors. Data transmitted to or from an I/O device, processor or memory is temporarily stored in a buffer within the memory controller. The buffers contain multiple addresses with each address capable of containing a quadword of data. The quadwords of data are transferred to the addresses corresponding to which quadword is the requested quadword from the processor. The quadwords are transmitted, requested quadword first then the next quadword, continuing until all quadwords are transmitted. The corresponding addresses are determined through incrementing or decrementing a pointer to the corresponding addresses, dependent upon the burst ordering translation required.