Patents Represented by Attorney Volel Emile
  • Patent number: 6745321
    Abstract: A method and apparatus for harvesting problematic code sections that may cause a hang condition based on a hardware design flaw is presented. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, steps are employed by hardware and/or software to recover from a hang condition, such as flushing instructions dispatched to the plurality of execution units. Upon successful completion of hang recovery, a debug interrupt is injected, causing a debug interrupt handler to be immediately involved before the resumption of normal execution. The debug interrupt handler may then harvest problematic code sections in the undisturbed execution error that may have caused the hang condition.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: June 1, 2004
    Assignee: International Business Machines Corporation
    Inventors: Michael Stephen Floyd, Kevin Franklin Reick
  • Patent number: 6744452
    Abstract: A modified web browser application on a data processing system for use in searching the Internet and displaying web pages. The modified web browser has a cache area which caches/stores a copy of a web page downloaded from the internet. When a particular page is requested, logic components within the modified web browser determine if the particular page is resident in the cache area. If the particular page is resident in the cache area, it is displayed within the modified web browser with an indicator by which the user is notified that the particular page displayed is cached. In one embodiment, the indicator is a cache message button which is displayed within the we browser. In another embodiment, the indicator is a color coded scheme which causes the web page or web page border to be displayed in a different color whenever the particular page is cached.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: June 1, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gerald Francis McBrearty, Shawn Patrick Mullen, Johnny Meng-Han Shieh
  • Patent number: 6738082
    Abstract: A graphical user interface for use in a data processing system for facilitating data entry for cluster analysis. In a preferred embodiment, the graphical user interface includes a source card list area, a participants area, a first sort area, and a second sort area. The source card list area allows entry, display of, and direct manipulation access to all of a plurality of items to be sorted. The participants area allows entry and display of participant names. The first sort area includes a plurality of first sections that each can contain a set of items dragged from the source card list area and represents a first-level of grouping of the items from the source card list area. The second sort area includes a plurality of second sections. Each of the plurality of second sections may contain items dragged from at least one of the first sections and represents a second-level of grouping of the items from the source card list area.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: May 18, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jianming Dong, Shirley Lynn Martin
  • Patent number: 6738909
    Abstract: A method and apparatus for use in data processing system for selecting rules to filter data for a tunnel. A request is received to create a tunnel to another data processing system. A granularity of information about the data processing system is identified to form an identified granularity. The identified granularity of the information about the data processing system is used to select a rule, which matches the identified granularity. This rule is placed in a filter, wherein the filter associates data packets with the tunnel.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: May 18, 2004
    Assignee: International Business Machines Corporation
    Inventors: Pau-Chen Cheng, William Alton Fiveash, Vachaspathi Peter Kompella, Christiaan Blake Wenzel, Jacqueline Hegedus Wilson
  • Patent number: 6735769
    Abstract: Apparatus and methods for initial load balancing in a multiple run queue system are provided. The apparatus includes a controller, memory, initial load balancing device, idle load balancing device, periodic load balancing device, and starvation load balancing device. The apparatus performs initial load balancing, idle load balancing, periodic load balancing and starvation load balancing to ensure that the workloads for the processors of the system are optimally balanced.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: May 11, 2004
    Assignee: International Business Machines Corporation
    Inventors: Larry Bert Brenner, Luke Matthew Browning, Mysore Sathyanarayana Srinivas, James William VanFleet
  • Patent number: 6728718
    Abstract: A system in which a DHCP server executes a recovery routine after detecting a corrupted IP address state database. The routine determines whether an IP address is assigned to a DHCP client by querying an IP address/port reserved for DHCP clients. If the response suggests the absence of a DHCP client, the address is marked as BAD. If the response suggests the presence of a DHCP client, the IP database is updated appropriately. The query may comprise sending a TCP/IP packet to the IP address and port and monitoring for an ICMP error message. In another embodiment requiring a protocol extension, the DHCP server issues a DHCP supported query to each IP address that responds to a ping command. The DHCP clients supporting this protocol extension will respond to the query by returning all of the DHCP configuration information that was acquired before the IP address state database crashed.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: April 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: Dwip N. Banerjee, Vinit Jain, Vasu Vallabhaneni
  • Patent number: 6728675
    Abstract: There is provided a user friendly display interface system for the interactive handling and sorting out of windows in complex window hierarchical graphical user interfaces. The system provides for the storage of a hierarchy of windows which are displayable to overlap each other in a selected order whereby a plurality of said windows are partially visible. Apparatus is provided for displaying on a display screen a plurality of these partially overlapping windows. A different audio identifier is provided and stored for each of these windows. Further apparatus is provided for moving around and positioning a pointing device, such as a cursor on the display screen, in combination with means responsive to the pointing device for announcing the audio identifier for each window which said pointing device enters. The pointing device may be a user controlled cursor, a stylus or even a finger in touch sensitive display systems. The audio identifier may conveniently be the name in the title bar of the window.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: April 27, 2004
    Assignee: International Business Machines Corporatiion
    Inventors: John Maddalozzo, Jr., Gerald Francis McBrearty, Johnny Meng-Han Shieh
  • Patent number: 6728866
    Abstract: A microprocessor and method of processing instructions for addressing timing assymetries are disclosed. A sequence of instructions including a first instruction and a second instruction are received. Dependency logic determines if any dependencies between the first and second instructions. The dependency logic then selects between first and second issue queue partitions for storing the first and second instructions pending issue based upon the dependency determination, wherein the first issue queue partition issues instructions to a first execution unit and the second issue queue partition issues instructions to a second execution unit. The first and second issue queue partitions may be asymmetric with respect to a first register file in which instruction results are stored. The first and second instructions are then stored in the selected partitions.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Charles Roberts Moore
  • Patent number: 6725405
    Abstract: An apparatus and method for performing a diagnostic problem determination methodology for complex systems is provided. With the apparatus and method, a diagnostic application for a system may automatically invoke additional diagnostics for child devices and/or siblings of the child devices based on status of the child devices after testing the parent device. This allows for complete testing of a subsystem in a single diagnostic execution resulting in a more complete, accurate analysis of subsystems with complex configurations such as seen with redundant arrays of independent disk drive (RAID) systems.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Pamela Ann Batten, Douglas Marvin Benignus, Arthur James Tysor
  • Patent number: 6725354
    Abstract: A microprocessor includes a first processor core and a second processor core. The first core includes a first processing block. The first processing block includes an execution unit suitable for executing a first type of instruction. The second core includes a second processing block. The second processing block includes an execution unit suitable for executing an instruction if the instruction is of the first type. The processor further includes a shared execution unit. The first and second processor cores are adapted to forward an instruction to the shared execution unit for execution if the instruction is of a second type. In one embodiment, the first type of instruction includes fixed point instructions, load/store instructions, and branch instructions and the second type of instruction includes floating point instructions.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Charles Roberts Moore
  • Patent number: 6725358
    Abstract: A processor includes a register set, at least one execution unit that executes load instructions to transfer data into the register set, a load queue and associated queue management logic. The load queue contains a plurality of entries that each include a reservation valid field, and each of the plurality of entries is associated with a respective one of a corresponding plurality of load instructions that includes at least one load-reserve instruction. In response to execution of the load-reserve instruction, the queue management logic detects whether a data hazard exists by reference to the load queue, and if so, initiates correction of the data hazard. In addition, the queue management logic records a reservation for the load-reserve instruction by setting the reservation valid field of an entry in the load queue associated with the load-reserve instruction.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventor: Charles Robert Moore
  • Patent number: 6721901
    Abstract: A method and system for recovering mirrored logical data volumes within a computer system after a system failure is disclosed. A computer system includes mirrored logical volumes that can be accessed by multiple nodes. Mirrored in-flight logs are provided for the mirrored logical volumes. The mirrored in-flight logs include multiple node partitions, each node partition corresponding to one of the nodes. Furthermore, each entry within the mirrored in-flight logs indicate whether or not a write operation is currently being performed by at least one of the nodes. After an abnormal termination of one of the nodes due to, for example, a system failure, one of the remaining nodes is automatically selected to copy data from one of the mirrored logical volumes to another of the mirrored logical volumes, according to the entries within one of the mirrored in-flight logs.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: April 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gerald Francis McBrearty, Johnny Meng-Han Shieh
  • Patent number: 6717528
    Abstract: A system and method for providing dynamic feedback projection from a hand held pointing device is provided. The system includes a hand held pointing device that is capable of two way communication with appliance interfaces associated with appliances that are controllable by the hand held pointing device. The hand held pointer is capable of transmitting signals to the appliance interfaces and receiving response signals from the appliance interfaces. The hand held pointing device further includes a visible light projection apparatus for projecting light onto a remote surface. The projected light is displaced on the remote surface by a light projection modification apparatus such that the projected light creates images corresponding to the response signals from the appliance interfaces.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Winslow Scott Burleson, David Lu, John Martin Mullaly
  • Patent number: 6717591
    Abstract: For a presentation comprising a plurality of presentation segments, timing is established through the combination of assigning a portion of a total presentation time to each of the plurality of presentation segments, displaying the time assigned to each of said presentation segments, enabling a user to change the time assigned to the segment being presented, and in response to a change in said time, dynamically reapportioning the remaining total time among the subsequent sequential presentation segments. The reapportioned times for said subsequent sequential presentation segments can further be displayed. There may also be means, responsive to the change in the time, for dynamically eliminating one of said sequential segments. In slide presentations, there may be means for displaying the reapportioned times for said subsequent sequential individual slides together with miniaturizations of each of said subsequent sequential individual slides.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: William Alton Fiveash, Denise Marie Genty, Gerald Francis McBrearty, Shawn Patrick Mullen, Johnny Meng-Han Shieh
  • Patent number: 6715062
    Abstract: A processor includes instruction sequencing logic, execution circuitry, data storage coupled to the execution circuitry, and test circuitry. The test circuitry detects for a hardware error in one of the instruction sequencing logic, execution circuitry, and data storage during functional operation of the processor in response to an instruction within an instruction stream provided by the instruction sequencing logic. In one embodiment, a hardware error can be detected by comparing values output in response to a test instruction by redundant circuitry that performs the same function. Alternatively or in addition, a hardware error can be detected by performing an arithmetic or logical operation having a known result (e.g., multiplication by 1, addition of 0, etc.) in response to the test instruction.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: March 30, 2004
    Assignee: International Business Machines Corporation
    Inventor: Charles Robert Moore
  • Patent number: 6704860
    Abstract: A data processing system and method of fetching instructions in a data processing system are described. The data processing system includes at least one execution unit that executes fetched instructions and instruction sequencing logic that fetches instructions from memory. In response to detection of a particular instruction trigger within an instruction stream, the instruction sequencing logic fetches one or more non-sequential blocks of instructions from memory, where each of the non-sequential blocks includes a plurality of instructions.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventor: Charles Robert Moore
  • Patent number: 6704926
    Abstract: A process in a data processing system for just-in-time compiling instructions. A set of non-specific data processing system instructions for a method are received. Addresses are placed into a set of functions. The set of non-specific data processing system instructions are processed using an intermediate code generation process to generate a set of instructions for execution using a particular mode of addressing.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey Owen Blandy, Andrew Johnson
  • Patent number: 6701416
    Abstract: A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: March 2, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6697851
    Abstract: A method and apparatus in a distributed data processing system for selecting configuration information for a client in the distributed data processing system. A request is received at a server from the client for configuration information. A subnet for the client is identified using the configuration information. A set of identification tokens is identified from the request. A plurality of containers in a hierarchical structure is traversed using the subnet and identification tokens to identify selected containers within the plurality of containers matching the subnet and the identification tokens. The identified containers are selected in an order the preserves preference as determined by their arrangement in the hierarchical structure and by the data that each contains. Configuration information is obtained from selected containers within the plurality of containers to form selected configuration information. The selected configuration information is sent to the client.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: February 24, 2004
    Assignee: International Business Machines Corporation
    Inventors: Gregory Scott Althaus, David Alexander Babbitt
  • Patent number: 6697939
    Abstract: A processor, data processing system, and a related method of execution are disclosed. The processor is suitable for receiving a set of instructions and organizing the set of instructions into an instruction group. The instruction group is then dispatched for execution. Upon executing the instruction group, instruction history information indicative of an exception event associated with the instruction group is recorded. Thereafter, the execution of the instruction is modified responsive to the instruction history information to prevent the exception event from occurring during a subsequent execution of the instruction group. The processor includes a storage facility such as an instruction cache, an L2 cache or a system memory, a cracking unit, and a basic block cache. The cracking unit is configured to receive a set of instructions from the storage facility. The cracking unit is adapted to organize the set of instructions into an instruction group.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: February 24, 2004
    Assignee: International Business Machines Corporation
    Inventor: James Allan Kahle