Abstract: An error generator for use with a memory device, such as dynamic random-access memory (DRAM) which is connected to an error detection or correction device, such as a memory controller using error-correcting code. The memory error generator uses a clock signal provided by the computer system, determines when the computer system first attempts to read from a data stream after synchronization, and thereafter introduces the error in at least one bit of the data stream by complementing the bit. The error generator can be provided with a switch such that synchronization is performed in response to activation of the switch. The error generator preferably is constructed using an inexpensive device, such as a programmable array logic (PAL) circuit. Use of a PAL allows the bit complementing to occur quickly enough to meet timing requirements of the memory controller. The PAL and switch can be mounted on an interposer which is removably connected to the memory array and the memory controller.