Abstract: A processor and disk controller are arranged to operate with either of two types of disk drive, a drive for a five and one-fourth inch disk or a drive for an eight inch disk, and a method and apparatus are provided to test a port to detect which type disk is connected. The disk drives do not directly signal their type, and in one operation this information is derived from "drive ready", signals that are supplied separately by each disk type. In an alternative method and apparatus, this information is derived by a test in which the clock speed is changed.

Abstract: A channel subsystem with a conventional serial extender link that causes communications between a channel and a control unit to be delayed by the additional time to transmit a message in one direction and to transmit an acknowledgement in the other direction. The channel subsystem also has a buffer and associated components (called a channel outboard box) that are used for prefetching data from processor memory or from a peripheral device without waiting for the acknowledgment routines that are commonly used on both an interlocked data transfer and a non-interlocked transfer (called data streaming). A system of counters and other components and associated operations maintain the correct byte count that would otherwise be maintained in a system without the prefetch buffer and with only a short serial link. A system of count and status frames provides for sending byte count and other status information between the channel and the outboard box.

Abstract: An improved TCM-like circuit module for cooling an array of chips mounted on a substrate. The substrate and the chips are enclosed by components that include a barrier plate that separates the chip space from a coolant such as air or chilled water. A floating plate contacts a heat transfer surface of each chip and forms a local heat sink. Pins conduct heat from the floating plate. In one embodiment, one end of each pin is rigidly attached to the floating plate and the other end is located in a cavity in the barrier plate. In a second embodiment, the cavities are formed in the floating plate and the barrier plate rigidly supports the pins. In the second embodiment, the pins can be extended through the barrier plate to contact the coolant directly.

Abstract: A circuit module that contains a planar array of chips has an improved fin assembly that transfers heat to a liquid coolant that is circulated through the fins in a single pass so that there is a tendency for the upstream edge of the fins to run cold and the downstream edge to run hot. The module can be immersed in the coolant. A shroud on the fins confines the coolant flow to channels defined by the fins, the shroud, and the base of the fins. The fin assembly is constructed so that the coolant channels are narrowed as a function of the temperature of the liquid coolant. The narrowing channels increase the coolant velocity and thereby improves the heat transfer at what would otherwise become the hot end of the module. The coolant velocity is increased at the appropriate rate to maintain equal cooling along the direction of coolant flow.

Abstract: A circuit for allocating main memory cycles between two data processors has means for making the allocation by either of two procedures. In one procedure, control of memory is transferred only after a request for memory access has been made. In a second procedure, transfer of memory control to a requesting processor is automatically accompanied by a request to return control. The control memory of a processor selects the process by two bits called Code Idle and Code Release. Code Idle accompanies instructions that usually mean that the releasing processor will not need memory for several memory cycle times, and an explicit request for transfer is made when memory is actually needed. Code Release accompanies instructions that do not require memory access at the time but are typically followed by a memory request within a processor cycle time or a few processor cycle times. Memory control is returned without the delay that is associated with an explicit request.

Abstract: Heat producing components such as semiconductor chips are arranged with a major heat transfer surface at an angle of about 10 degrees to the vertical. A film of a dielectric liquid flows downward across this surface from a catch pan located above the component. The film evaporates and thereby removes heat from the component and the vapor is condensed and returned to the catch pan. The angle of the heat transfer surface helps to prevent separation of the film as it flows downward across the surface. In one embodiment the slanting surface is formed by slanted grooves in an otherwise vertical surface of a semiconductor chip. In other embodiments, a slanting surface or a vertical surface with slanting grooves is formed in place on the chip or is formed separately and attached to the chip or is formed as part of a local enclosure for the chip.

Abstract: Data is transferred between a channel and a control unit in interlocked mode or in data streaming mode over a conventional parallel bus and a serial link that permits the control unit and the channel to be located farther apart than the length of the parallel bus. The serial link carries frames for the rise of the data transfer tags but not their fall, and these tags on the parallel bus are dropped by two circuits that connect the serial link to the parallel bus. In data streaming mode, one data transfer tag is dropped when the next data transfer tag is received on the serial link. The circuit at the control unit end of the serial link detects a pause in the tags to begin an operation to drop the last data transfer tags and both circuits respond to other conditions to drop the last data transfer tags according to the protocol of the parallel bus.

Abstract: A metal foil for use as a heat transfer element has through holes formed as a narrow entrance opening to one surface and a wider diameter cavity opening to the other surface. Two foils are laminated with the narrow entrances opening to the outside and with the wider cavities closed by the inside surface of the other foil. In the completed structure the cavities and their entrances form nucleate boiling sites. In a manufacturing step of forming the through holes, the junction between the narrow entrance and the wider diameter cavity is shaped to prevent a heat transfer liquid from flooding the cavities. The structure is particularly useful for fins for cooling circuit devices that are immersed in a dielectric liquid. In one heat transfer structure, the fins are formed by laminating two metal foils that have differing coefficients of thermal expansion. The fins spread apart as their temperature increases, and components are cooled in proportion to the heat they produce.

Abstract: A data buffer has a storage array that is addressable for read and write operations by an address of n bits that are supplied by a read address counter and a write address counter that each have n+1 bits. The n+1th bit is in effect a counter for passes through the array by the read and write circuits. During a write operation the n+1th bit of the write counter is stored as part of a parity bit for the addressed array location. During a read operation the n+1th bit of the read address counter is entered into a parity checking function on the word read from the addressed location. An errror is signaled if the n+1th bit of the read address counter does not agree with the n+1th bit of the write counter at the time of the write operation. For example, an error is detected if the write circuits fail and the read circuits make a second pass through words that have previously been read. The same entries on a next pass through the array.

Abstract: In a data processor having a paging system, a list is kept of the disk seek time when a page of information is brought into processor memory from a disk storage device. (Seek time is the time for moving the disk read-write head radially inward or outward to the next track that is to be accessed.) The average seek time for the pages in memory is calculated and is compared with a reference value of seek time. When the average reaches the reference, the pages in memory are reordered on the disk. This reordering takes place as the pages are bumped from memory in the normal process of paging, and the pages are relocated on the disk tracks in the physical order in which the pages were originally brought into memory. If approximately the same pages are fetched again in approximately the same sequence, the read-write head of the disk drive will be moved a shorter distance between successive disk accesses with reduced backtracking.

Abstract: A priority circuit handles requests by three components of a data processing system for access to several resources of the system that can be accessed one at a time on each operating cycle of the system. A logic circuit receives requests by the requesters and grants access to one requester on a priority basis. The logic circuit has means for establishing a particular priority sequence, and the priority circuit includes means for stepping the logic circuit through a cycle of different priority sequences. In a repeating cycle of these steps, each requester is given the highest priority at least once. In a specific embodiment, the stepping means is a counter and a cycle is called a counting cycle. The stepping means is responsive to a control code to establish a particular stepping sequence.

Abstract: Several I/O channel processes time share a data pipeline processor. For each stage of the pipeline, there is a control memory and means for shifting an address from memory to memory as a process in the pipeline proceeds from stage to stage. The number of processes is greater than the number of pipeline stages, and storage is provided for the data and for the addresses while a process is out of the pipeline, waiting to be re-entered for a next pass. A storage array for holding the addresses is arranged to hold addresses for four activity levels for each process. While an address is held in the array it can be modified for the next pass through the pipeline or the process can be switched from a lower priority level activity to a higher level activity.

Abstract: Heat conducting pins are mounted on a base to be cooled and carry heat conducting wings that extend oppositely in the upstream and downstream direction of the flow of a coolant across the base. The wings are generally trapezoidal in shape, and they produce a greater drag on the coolant flow along the longer edge of the trapezoid shape than along the shorter edge. The pins along a column of coolant flow are oriented with the shorter parallel edges of the wings alternately at the base or at the top of the pin. The alternating regions of high drag and low drag produce an up-down motion in the coolant flow that improves heat transfer.

Abstract: A channel communicator CC has a storage array for holding an entry for each channel and for holding a busy vector and an interrupt vector that each have a bit for each channel. The CC is connected between the input bus and the output bus that connect the channels and an I/O processor IOP to processor main store. A message to the CC includes the ID of the channel that the message is to or from and the CC uses this ID as an address for accessing a channel entry or a bit in a vector. The message also carries a command that controls the CC to store a data portion of a message or to fetch a channel entry or a vector from the array and load it onto the output bus addressed to the IOP or to one of the channels. The command also controls addressing a particular one of the vectors. The CC also has means responsive to a command to perform a sequence of operations for testing the vectors and for testing fields of an entry in the array and for using the results of the test to control the execution of the command.

Abstract: A display system has a driver program for displaying alphanumeric characters and a driver program for displaying graphics. When a graphics window is opened, a program in the operating system establishes a control block containing a code that has been made unique within the user's program. For operations within a window, a function packet is passed to the appropriate driver. The operations are identified by the unique code and several independent windows can be created.

Abstract: A PLA is constructed to improve random testing. Section circuits are provided that permit disabling sections of the output lines that are called segments so that the circuit can be tested one segment at a time. Selection circuits are also provided for enabling the product term lines only one at a time. Thus, while random test signals are conventionally applied to the PLA input terminals for test, only a small portion of the PLA is enabled for the test. Control signals for the selection circuits are generated randomly so that the portion of the PLA that is tested is varied randomly.

Abstract: In a communications system in which voice is transmitted as packets of digitized samples, a receiving station delays the output of the first packet in a way that compensates for wide variations in the intervals at which successive packets are received. According to one feature of this system, a first packet is transmitted at a higher priority so that a greater delay can be used without encounter problems that arise from the uncertainty in the delay in transmitting this packet. In another feature of this system, the arrival time of the first few packets of a conversation are detected and the delay is readjusted in case the first packet has been unusually delayed.

Abstract: An electronic assembly with forced convection cooling comprises an elongate support plate having a plurality of electronic equipment cabinets mounted side by side on a common surface of the plate in the longitudinal direction thereof. At least one air distribution channel extends longitudinally of the plate in the said common surface, and a cooling fan is mounted on the same surface of the plate as the cabinets for forcing air along the air distribution channel and into the cabinets for cooling electrical components therein.The assembly preferably includes means for directing air from the channel selectively in different quantities to different components according to their cooling requirements, such means including a plurality of secondary air distribution channels which branch laterally from the first mentioned channel, and means for confining air from the first mentioned channel to flow into the secondary channels.

Abstract: A channel for a data processing system is provided with a time of day clock that is synchronized with the time of day clock of the associated central processor. Both the central processor and the channel processor record times of particular events, and the channel uses these times to calculate two times called Function Pending and Function Active. Both times begin when the central processor executes an instruction to begin an I/O operation. Function Pending ends when the channel has made successful initial selection. This time shows delays by the channel processor in scheduling the channel control unit, and device resources for I/O operations. Function Active ends at Channel End. A new instruction, Set Channel Monitor, enables or disables these measurements. An information block for each subchannel defines one of several measurement modes for a subchannel or disables the subchannel from measurement.