Abstract: Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserved memory area associated with the currently active operating system is then addressed and register contents of a central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory and, data establishing the decor of the operating system being activated are entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun.

Abstract: A phase-locked loop is implemented using strictly digital techniques. The average frequency of the input signal is first sampled by counting the number of pulses from a clock source which occur during a predetermined number of occurrences of the input signal. Thereafter, the number of pulses counted is divided by the number of cycles of the input signal which occurred during the counting period to determine an average number of pulses per input signal cycle. The number of pulses which occur between successive cycles of the input signal are then counted and compared against the previously determined average. A count which differs from the average indicates a change in phase of the input signal, and after appropriate weighting, is used to update the average to a new average. An output signal is produced when the number of pulses counted during a cycle of the input signal equals the average number of pulses determined to occur between successive cycles of the input signal.

Abstract: A sequencer control for controlling the time sequencing of the energization of controlled elements includes a microprocessor unit. A large number of input lines and output lines are uniquely multiplexed into a relatively small number of I/O terminals on the microprocessor. The multiplexing, the sequencing and all of the delays are effectively controlled by the microprocessor.

Abstract: Apparatus for determination of direction using the curl-free magnetic vector potential field. The apparatus includes apparatus for generating a predominantly curl-free magnetic vector potential field with a predetermined vector field spatial orientation. The field receiving apparatus includes a detecting apparatus with observable properties that vary with magnitude and orientation of an applied curl-free magnetic vector potential field. The apparatus can specify a direction of the field generating apparatus. A periodically rotating vector field can specify a path toward the field generating apparatus. The curl-free magnetic vector potential field can be established in conducting and opaque materials which are not capable of transmitting normal electromagnetic radiation.

Abstract: The present invention relates to a power sequence device which comprises an element which generates a sequencing code which is capable of being decoded by actuators included in the various equipment cabinets. The sequencing code is initiated by a sensing element which indicates the input power has reached a stable threshold whereupon the various cabinets comprising the data processing system are turned on in a desired order. Upon loss of power, the sensing element generates a warning signal indicating an impending power loss thereby enabling the equipment to perform an orderly halt.

Abstract: A short term response enhancement for a digital phase-locked loop is implemented to provide a relatively major change in the phase of the output signal over a relatively short period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur, producing an output signal when the two numbers agree. The number of pulses which occur between successive cycles of the input signal are also compared against the previously determined average. A count which differs from the average count indicates a change in phase of the input signal.

Abstract: A system for determining the modulation imposed on a curl-free magnetic vector potential field. The system includes apparatus for detecting the curl-free magnetic vector potential field component by means of a Josephson junction. The magnetic vector potential field interacts with the Josephson junction by varying the phase of the argument of the sine function which determines the Josephson junction current. The output signals of the Josephson junction are coupled to apparatus that can determine the modulation of the detected field. Because the magnitude of the change in the detected curl-free vector potential field causes a proportional change in the phase of the Josephson junction current, the modulation of the field can be established.

Abstract: Apparatus for producing and modulating a magnetic vector potential field having a substantially curl-free component. Detection and demodulation of the curl-free component of the magnetic vector potential field using a Josephson junction device are described of the curl-free magnetic vector field. Examples of modulation of the curl-free magnetic vector field suitable for detection and demodulation by the Josephson junction device are disclosed.

Abstract: Apparatus for entering encoded data, command, and address information via a keyboard for transfer to an automated maintenance system designed to perform certain tests on or cause selected events in a unit of a data processing system such as the central processing unit. The data, command and address information entered via the keyboard by an operator serves to control the tests performed by or the events caused by the automated maintenance system. The maintenance panel also includes a plurality of display devices for displaying the data, command and address information sent to the automated maintenance system as well as data received by the automated maintenance system from the unit under test indicating the correctness of its performance. In the preferred embodiment, several LED indicators are also used for prompting and status indication.

Abstract: A transport system for transporting fixtures adapted to hold a workpiece sequentially from a fixture transferor station to a fixture transferee station. A fixture guide rail interconnects the two stations and is provided with a chain guide recess that extends from one station to the other. A continuous plastic timing chain cable is mounted on a plurality of sprockets so that the chain can be made to rotate. The sprockets are positioned so that the timing chain is positioned in the chain guide recess. Drive pins are mounted in selected ones of the links of the chain so that the pins will project from one side of the chain. The drive pins initially contact a fixture positioned in the transferee station and move each fixture, in turn, along the guide rails to the transferee station. A drive motor is connected to one of the sprockets to cause the sprocket to move the chain. The distance between drive pins is substantially constant and greater than the corresponding dimension of the fixtures being transported.

Abstract: This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system.The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting apparatus, the operation in progress is aborted if an error has been detected and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted.Two, three state busses are employed. The first, three-state data bus is used to transmit memory data to the error detection and correction (EDAC) circuitry and to the data output circuits and to transmit input data to the memory. The second three state data transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from the data output circuits to the instruction buffer.

Abstract: An apparatus for conducting input output operations with another data processing device in a flexible and low cost manner is comprised of a programmed microprocessor coupled to a keyboard, a parallel port, and a modem. The microprocessor is programmed to periodically scan the keyboard to determine what keys if any are depressed. It also scans the parallel port for incoming data and senses incoming data from the modem by sensing a start bit. Control characters from the keyboard can set options such that incoming data from an input can be simultaneously sent out from the modem and/or parallel port.

Abstract: This relates to a fiber optics communication link, wherein a single optical fiber carries data bi-directionally between two computers. The first computer is coupled by means of control logic to a first transmitter and a first receiver. The first transmitter and receiver are in turn coupled to a single optical fiber by means of a Y-coupler. A second computer is similarly coupled via control logic to a second transmitter and second receiver, which is in turn coupled to the single optical fiber by means of a second Y-coupler. To minimize problems due to reflections, each receiver is disabled when its corresponding transmitter is transmitting data.

Abstract: An integrated circuit package in which an integrated circuit chip having flexible beam leads, the inner lead bonding sites of which are bonded to input and output terminals on the active face of the chip, is mounted active face down on the top surface of a substrate. The top surface of the substrate is provided with a chip pad on which the integrated circuit chip is mounted and outer lead pads. The back surface of the substrate has a heat sink pad which is positioned substantially opposite the chip pad. A plurality of thermal passages is formed through the substrate interconnecting the chip pad and the heat sink pad. A good thermally conductive material fills the passages. A preform comprising a segment of fiber glass web coated with a thermosetting and thermally conductive plastic is positioned on each chip pad between the chip pad and the active face of the integrated circuit chip.

Abstract: The method of mounting on a substrate an integrated circuit (I.C.) chip having flexible beam leads bonded to input/output (I/O) terminals on the active face of the I.C. chip. The substrate has a chip pad and outer lead (OL) pads associated with the chip pad on a surface of the substrate. Preforms of a fiber glass web coated with a thermosetting plastic are cut to a size that substantially conforms to that of the chip pad. The substrate and the chip pad are heated to a first temperature which the preform will adhere to the chip site, the preform is placed on the chip pad, and the active face of the I.C. chip is pressed into the preform. The temperature of the substrate, preform and chip, are then raised to a second temperature higher than the first to partially cure the thermoplastic material and to encapsulate the active face of the I.C. chip and portions of the leads proximate the chip in the thermoplastic material of the preform. The I.C.

Abstract: An apparatus and method for decoding input signals on four lines to produce an outgoing information stream of binary bits.

Abstract: A collision avoidance apparatus having a voltage source producing a predetermined voltage level. A switching network within the collision avoidance apparatus is capable of alternately applying the predetermined voltage level to the communication medium and of applying the voltage level of the communication medium to a logic network. The logic network indicates if the predetermined voltage level and the voltage level of the communication medium are approximately equal.

Abstract: Two switching elements are cross-coupled in the standard bistable multivibrator arrangement. Two additional switching elements are added: one each in parallel with one of the switching elements forming the bistable multivibrator. The two wave forms under study are applied to the control gate of each of the additional switching elements. When both wave forms are in one state, the two additional switching elements are switched ON, effectively inhibiting bistable multivibrator action. The first wave form to change state results in its associated switching element switching OFF, which releases the bistable multivibrator circuit to assume the corresponding stable state, which observed differentially across the switching element forming the bistable multivibrator, is indicative of the wave form to first undergo transition.

Abstract: A slowly varying bias signal is added to one input of a Wave Form Transition Sequence Detector, as more fully described in a related application cited herein, to provide a differential output therefrom which is directly proportional to the time between transitions occurring on two input wave forms. The slowly varying bias modulates the level of one input wave form, and thereby varies the time required for the Wave Form Transition Detector to detect a transition occuring thereon. By symmetrically varying the response time of the Wave Form Transition Sequence Detector to one input wave form in the neighborhood of the occurrence of a transition on the second input waveform, the average differential output of the Wave Form Transition Sequence Detector over a cycle of the slowly varying bias level will be proportional to the time between transitions occurring on the two input wave forms.

Abstract: A clock pulse driver has applied to it a system clock pulse signal, or system clock and produces a first set of individually enabled clock pulse signals, the leading edges of the pulses of which substantially coincide with the leading edges of the pulses of the system clock, a second set and a third set of clock pulse signals, the trailing edges of the pulses of which substantially coincide with the leading edges of the pulses of the system clock. The width of the pulses of the three sets of output signals are controllable by first, second and third delay pulse signals. The clock pulse driver also produces delay signals the pulses of which have a predetermined relationship to the pulses of the system clock which delay signals can be used to control the widths of the first, second and third sets of clock signals produced by the driver circuits, and to control the delay or offset of the first, second and third sets of clock signals produced by the driver circuit.