Abstract: A method and apparatus for measuring alternating current (AC) and direct current (DC) characteristics of a plurality of semiconductor devices. A ring oscillator generates pulses to drive the plurality of semiconductor devices under test. Current/Voltage (IV) and transfer characteristics of the plurality of semiconductor devices are measured using only DC input/output.

Abstract: In a FinFET integrated circuit, the fins are formed with a reduced body thickness in the body area and then thickened in the S/D area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the lower portion of the gates are covered by a gate cover layer to prevent thickening of the gates at the fin level, which may short the gate to the S/D.

Abstract: A method and apparatus for monitoring a plurality of semiconductor devices is disclosed. At least one array of 2n semiconductor circuits is provided. A clock ring oscillator provides a clock signal. The clock signal drives a frequency divider followed by an n-stage binary counter. The outputs from the counter's stages drive an n-input decoder which sequentially addresses each semiconductor circuit. An output signal from each semiconductor circuit is measured and read out over a common bus, where a distribution of the output signals is a measure of a distribution of a parameter of interest.

Abstract: The present invention is a method and an apparatus for thermo-optic control of optical signals using photonic crystal structures. In one embodiment, a first portion of a split signal is modulated by propagating the signal through a photonic crystal waveguide in which two electrical contacts are laterally spaced from the waveguide region by a plurality of apertures formed through the photonic crystal substrate. A voltage applied across the electrical contacts causes resistive heating of the proximate photonic crystal waveguide through which the signal propagates, thereby modulating the temperature relative to an un-modulated second portion of the split signal that is used as a reference.

Abstract: A thermal interface for IC chip cooling is provided. One embodiment of the thermal interface includes a thermally conductive liquid or paste-like metal(s) disposed within a flexible, thermally conductive enclosure. The enclosure is adapted to be placed between an IC chip and a heat sink to enhance heat transfer from the chip to the heat sink, thereby enabling quicker and more efficient cooling of the chip than can be achieved by conventional techniques. In several embodiments, the thermal interface is held in place by mechanical pressure rather than by bonding, which further facilitates inspection and repair of the IC device.

Abstract: One embodiment of the present method and apparatus for detecting leaks in a fluid cooling system enables a user to rapidly detect fluid leaks in the vicinity of a microprocessor chip or other delicate item. In one embodiment, the invention comprises a detector and a border coupled to the detector and disposed peripherally about a protected item (e.g., the microprocessor chip or other delicate item). In one embodiment, the border is a layered structure that is adapted to complete an electrical circuit with the detector when the border comes into contact with fluid.

Abstract: Described is an electronic device comprising a junction formed between a first fullerene layer having a first doping concentration and a second fullerene layer having a second doping concentration different from the first doping concentration. The first doping concentration may be zero. The first and/or the second fullerene layer may be a monolayer. The second fullerene layer may comprise an electron donor. One example of such a device is a diode wherein the first fullerene layer is connected to an anode and the second fullerene layer is connected to a cathode. Another example is a field effect transistor wherein the first fullerene layer serves as a gate region and the second fullerene layer serves as a channel region. The second fullerene layer may alternatively comprise an electron acceptor. At least one of the first and second fullerene layers may be formed from C60, or may consist of a single bucky ball.

Abstract: A method for protecting a material of a microstructure comprising said material and a noble metal layer against undesired galvanic etching during manufacture comprises forming on the structure a sacrificial metal layer having a lower redox potential than said material, the sacrificial metal layer being electrically connected to said noble metal layer.

Abstract: A valve comprising a housing having an inlet and spaced therefrom an outlet, a passageway extending between the inlet and the outlet, and a mechanism located in the passageway for controlling the flow of a fluid between the inlet and the outlet, the mechanism including a valve assembly movable between a first open position spaced from a co-operating valve seat and a second closed position at which the valve assembly sealingly engages the valve seat, in which the valve assembly is biased towards the second closed position using a magnet-operated mechanism.

Abstract: A system and method for controlling the rates at which application workload, e.g., TCP connection requests, is admitted to a collection of servers, such as a server farm of an application service provider (ASP) that hosts Internet World Wide Web (WWW) sites of various owners. The system and method are intended to operate in an environment in which each customer has a workload-based SLA for each type of application hosted by the provider and used by the customer. The system and method achieve support (minimum, maximum) TCP connection requests for multiple customers and applications. According to one aspect, the system and method guarantee, control and deliver TCP connection-based workload SLA's to customers whose applications are hosted by the server farm with the use of a workload regulator that operates by regulating only new TCP connection request packets while transparently passing existing TCP connection packets and other request packets received for customers.

Abstract: A highly scalable system and method for supporting (mim,max) based Service Level Agreements (SLA) on outbound bandwidth usage for a plurality of customers whose applications (e.g.,Web sites) are hosted by a server farm that consists of a very large number of servers. The system employs a feedback system that enforces the outbound link bandwidth SLAs by regulating the inbound traffic to a server or server farm. Inbound traffic is admitted to servers using a rate denoted as Rt(i,j), which is the amount of the ith customer's jth type of traffic that can be admitted within a service cycle time to servers which support the ith customer. A centralized device computes Rt(i,j) based on the history of admitted inbound traffic to servers, the history of generated outbound traffic from servers, and the SLAs of various customers. The Rt(i,j) value is then relayed to one or more inbound traffic limiters that regulate the inbound traffic using the rates Rt(i,j) in a given service cycle time.

Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

Abstract: The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.

Abstract: An optical receiver circuit including a plurality of PIN diodes, each associated with a dedicated element transimpedance amplifier, the outputs of the element transimpedance amplifiers being connected to a summing amplifier which sums the voltages output from the element transimpedance amplifiers. The optical receiver circuit provides the same output voltage value as a single large PIN diode having an active area comparable to the sum of the active areas of the smaller PIN diodes, and thus has the same high sensitivity as the single large PIN diode but a much wider bandwidth.

Abstract: A magnetic memory cell that uses a curved magnetic region to create magnetic anisotropy is provided by the present invention. The magnetic memory cell is created from a free magnetic layer, a barrier layer and a reference magnetic layer. The magnetic layers are constructed such that they have portions that are curved with respect to a first axis and straight with respect to a second perpendicular axis. These curved portions result in a magnetic memory cell that has an easy axis that is parallel to the first axis and a hard axis that is perpendicular to the easy axis. In addition, the resulting magnetic memory cell's coercivity is independent of it's thickness. Thus, the magnetic memory cell is well adapted to being scaled down without increasing the likelihood of thermally induced errors.

Abstract: The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

Abstract: A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.

Abstract: An electrically adjustable phase-shifting device is arranged on a substrate comprising at least a first waveguide designed for guiding optical signals and a thermoelectric element arranged adjacent to the first waveguide in order to shift the phase of an optical signal in the first waveguide by means of a thermo-optic effect according to a control voltage applied to the thermoelectric element. In one embodiment, the thermoelectric element is a Peitier element which comprises at least first and second electrically conducting segments which are serially connected, the first and second elements alternating consecutively.

Abstract: Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias.

Abstract: A magnetic random access memory circuit comprises a plurality of magnetic memory cells, each of the memory cells including a magnetic storage element having an easy axis and a hard axis associated therewith, and a plurality of column lines and row lines for selectively accessing one or more of the memory cells, each of the memory cells being proximate to an intersection of one of the column lines and one of the row lines. Each of the magnetic memory cells is arranged such that the easy axis is substantially parallel to a direction of flow of a sense current and the hard axis is substantially parallel to a direction of flow of a write current.