Abstract: A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.

Abstract: Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.

Abstract: Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: Selective deposition of metal over dielectric layers in a manner that minimizes of eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured as allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer.

Abstract: A gas sensitive material comprising SnO2 nanocrystals doped with In2O3 and an oxide of a platinum group metal, and a method of making the same. The platinum group metal is preferably Pd, but also may include Pt, Ru, Ir, and combinations thereof. The SnO2 nanocrystals have a specific surface of 7 or greater, preferably about 20 m2/g, and a mean particle size of between about 10 nm and about 100 nm, preferably about 40 nm. A gas detection device made from the gas sensitive material deposited on a substrate, the gas sensitive material configured as a part of a current measuring circuit in communication with a heat source.

Abstract: A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening.

Abstract: A thermoformed article stack segmenting apparatus is provided. The apparatus includes a frame, a stacked article guide channel, a forward engaging drive finger, a reciprocating actuator and a rearward engaging holding finger. The stacked article guide channel is carried by the frame and configured to receive and guide a stack of inter-nested articles exiting a female die of a thermoforming trim press. The reciprocating actuator is coupled with the finger to drive the finger forward in engagement with one separated stack of articles. The actuator also drives the finger rearward in a retractable state to separate another, successive stack of articles. The rearward engaging holding finger is supported by the frame and is configured to hold the another, successive stack while driving the forward engaging drive finger forward.

Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.

Abstract: This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated.

Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

Abstract: A position detection apparatus, with which the setting position adjustment of imaging sections is not required and the maintenance can be made easily, structuring of which can be realized with low-cost components, is provided. In the position detection apparatus, imaging sections (7), each of those which includes an area image sensor (70), in which light-sensitive elements are arrayed in a two-dimensional pattern, and an image formation lens (71), are placed to the lateral two points of a detection plane (1), respectively. A selection device (10) selects particular pixels corresponding to a particular field of view of a reflex reflection frame (4) or the like from the light-sensitive elements within a range of a given field of view having been imaged by the imaging sections (7). An image processing device (11) image-processes a particular image signal corresponding to the selected particular pixels and then outputs an indicating position coordinate of a pointing device (2).

Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.

Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.

Abstract: Some embodiments include methods of forming diodes. The methods may include oxidation of an upper surface of a conductive electrode to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of an oxidizable material over a conductive electrode, and subsequent oxidation of the oxidizable material to form an oxide layer over the conductive electrode. In some embodiments, the methods may include formation of a metal halide layer over a conductive electrode. Some embodiments include diodes that contain a metal halide layer between a pair of diode electrodes.

Abstract: Some embodiments include methods of forming metal-containing structures. A first metal-containing material may be formed over a substrate. After the first metal-containing material is formed, and while the substrate is within a reaction chamber, hydrogen-containing reactant may be used to form a hydrogen-containing layer over the first metal-containing material. The hydrogen-containing reactant may be, for example, formic acid and/or formaldehyde. Any unreacted hydrogen-containing reactant may be purged from within the reaction chamber, and then metal-containing precursor may be flowed into the reaction chamber. The hydrogen-containing layer may be used during conversion of the metal-containing precursor into a second metal-containing material that forms directly against the first metal-containing material. Some embodiments include methods of forming germanium-containing structures, such as, for example, methods of forming phase change materials containing germanium, antimony and tellurium.