Abstract: Improved efficiency of address/data communication over a memory bus. A memory-control device is located between a processor 30 and memory ranks 40a, 40b and controls access to the memory ranks 40a, 40b. A memory-management unit 10 receives and buffers access request from the processor 30 to memory ranks 40a, 40b, and issues access request to a rank-management unit 20 based on scheduling for memory management. A rank-management unit 20 connects the memory ranks 40a, 40b, receives and buffers access request from the memory-management unit 10, and gives access request to a specified memory rank based on scheduling for rank management.