Abstract: A timing signal generator of an MPEG video decoder is responsive to a picture type signal for selectively generating one of a timing signal for decoding I and P pictures and a timing signal for decoding a B picture within a predetermined period of time, permitting an increased speed for the B picture decoding.

Abstract: A shift register constituting a scanning pass test circuit is divided into a plurality of groups, and bypass selectors are inserted into the divided positions of the shift register. A latch circuit is connected to each of the clock signal terminals of the flip-flop circuits which are disposed at the first stage of the flip-flop circuit groups.

Abstract: A polyalkylmethacrylate co-polymer of polyhydroxystyrene has been found to be an ideal blending partner in a novolak photoresist composition. The preferred co-polymer is poly(p-hydroxystyrene)-co-(methyl methacrylate). The co-polymer is fully miscible with novolaks and has a high thermal stability (>150.degree. C.).

Abstract: Deformation of a lifting ring of bimetallic structure or memory metal is matched to a solder softening or melting temperature to apply forces to lift a chip from a supporting structure, such as a substrate or multi-chip module, only when the solder connections between the chip and the supporting structure are softened or melted. The temperature of the chip, module and solder connections there between is achieved in a commercially available box oven or belt furnace or the like and results in much reduced internal chip temperatures and thermal gradients within the chip as compared to known hot chip removal processes. Tensile and/or shear forces at solder connections and chip and substrate contacts are much reduced in comparison with known cold chip removal processes. Accordingly, the process is repeatable at will without significant damage to or alteration of electrical characteristics of the chip or substrate.

Abstract: A portable calculator for operating a calculation between arrays or between an array and a single operand has an array detecting section. The array detecting section identifies each of operands included in an arithmetic expression as a single operand or an element of an array including a plurality of elements, each successive two of elements in the array sandwiching a space and sandwiching no operator. The calculation is executed defined by the arithmetic expression between each of the elements of a single array and a single operand or between corresponding elements of a plurality of arrays.

Abstract: A multiprocessor system includes first and second microcomputers, a address decoding mechanism, and a ready signalling device. The address decoder is coupled to an address bus, to decode address information transferred by the second microcomputer, and supplies a request signal to a request signal input terminal of the first microcomputer. A bus control unit of the first microcomputer responds to the request signal to detect whether an internal bus of the first microcomputer is free from being used by the CPU, and outputs an acknowledge signal to an acknowledge signal output terminal when the internal bus is free. The ready signaling device is coupled to the acknowledge signal output terminal to supply the ready signal to a ready signal input terminal of the second microcomputer in response to the acknowledge signal outputted at the acknowledge signal output terminal and the request signal.

Abstract: Data communication equipment incorporating a matrix switch 11 and a control section 19 in which the matrix switch 11 is provided between M terminal interface units 12.sub.1 -12.sub.M and N communication channel interface units 13.sub.1 -13.sub.N and is capable of switching the combination of the N communication channels 10.sub.1 -10.sub.N and the M data terminal units 18.sub.1 -18.sub.M to enable mutual connections between a desired pair of communication channel and interface units. The controller 19 controls the matrix switch 11 and prescribes the appropriate connections between one of the N communication channel interface units 13.sub.1 -13.sub.N and one of the M terminal interface units 12.sub.1 -12.sub.M. Both the N communication channel interface units 13.sub.1 -13.sub.N and the M terminal interface units 12.sub.1 -12.sub.M are capable of inserting or extracting the connections to the matrix switch 11 on a unit-to-unit basis by means of a pair of N terminal groups 15.sub.1 -15.sub.

Abstract: A multi-prediction branch prediction mechanism predicts each conditional branch at least twice, first during the instruction-fetch phase of the pipeline and then again during the decode phase of the pipeline. The mechanism uses at least two different branch prediction mechanisms, each a separate and independent mechanism from the other. A set of rules are used to resolve those instances as to when the predictions differ.