Patents Represented by Attorney William B. Porter
  • Patent number: 4979105
    Abstract: A program executing on a first processor in an MP configuration awaiting the release of a resource held by another processor, detects the expiration of a fixed time interval, and initiates a hierarchy of recovery actions designed to cause the resource to be freed. These actions, targeted at a processor believed to be the one currently holding the resource, are taken only if that processor is not executing an "exempt" routine. The actions, taken in order of increasing severity, are: wait for a second fixed time interval; terminate the routine on the resource-holding processor, allowing retry; terminate the routine without allowing retry; invoke Alternate CP Recovery. The hierarchy is escalated against the target processor until that processor releases the resource, and against other processors in the configuration until the resource is acquired by the first processor. These actions may proceed in parallel for multiple detecting and target processors within an MP environment.
    Type: Grant
    Filed: July 19, 1988
    Date of Patent: December 18, 1990
    Assignee: International Business Machines
    Inventors: James C. Daly, Jeffrey M. Nick, Franklin J. Rodegeb
  • Patent number: 4866651
    Abstract: For successively adding a series of floating point numbers, a floating point adder stage (FIG. 2) is used which, in addition to the sum of two floating point operands, emits the remainder, truncated from the smaller operand, as a floating point number. For obtaining an exact sum of the operands, these remainders are summed in the form of intermediate sums. A circuit arrangement for parallel operation comprises series-connected floating point adder stages (FIG. 6), the intermediate sum occurring at the output of each stage and the intermediate remainder being buffered. Remainders are in each case passed on to the next stage, their value decreasing until they are zero. A serially operating arrangement (FIG. 8) comprises a single adder stage (30) and a register stack (34) for buffering the intermediate sums and the final result. A remainder occurring is stored in a remainder register (32) at the output of the adder stage and added to the intermediate sums until the remainder is zero.
    Type: Grant
    Filed: August 26, 1987
    Date of Patent: September 12, 1989
    Assignee: International Business Machines Corp.
    Inventors: J. Hartmut Bleher, Axel T. Gerlicher, Siegfried M. Rump, Dieter K. Unkauf
  • Patent number: 4823261
    Abstract: An apparatus and method employs dual checkpoint data sets for communicating system status. A journal of changed data is implemented to reduce I/O to a subsystem's shared data area on a non-volatile shared storage device. The journal provides for an increase in the amount of time that a processor may have access to the shared data area. Also, two versions of the data area are implemented in order to insure the integrity of the continuously updated data area. The two versions flip-flop depending upon which one has the most recent updates. That is, the version that has the most recent updates becomes the to-be-read-from data area and is read by the processor that currently has access to the shared data area during this series of I/O operations. The other version becomes the to-be-written-to data area and is written to by the processor that currently has access to the data area in order to update the to-be-written-to version to the current level.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: April 18, 1989
    Assignee: International Business Machines corp.
    Inventors: Judith H. Bank, Harry G. Familetti, Charles W. Lickel