Abstract: Implemented as a monolithic integrated circuit in CMOS technology, consisting of two two-transistor inverters cross-coupled to form a four-transistor flip-flop memory cell plus an A port NMOS gating transistor connected to one side of the flip-flop and a B port NMOS transistor connected to the other side of the flip-flop. Each A port and B port gating transistor is respectively independently gated by an A port word line and a B port word line addressing signals to conduct the stored contents of the flip-flop respectively to an A port bit line or a B port bit line. The data signal upon each A port bit line and B port bit line is respectively independently gated through respective NMOS transistors by respective A port column address line and B port column address line addressing signals to next be individually compared, in a complementary sense, to a set reference voltage in a respective A port sense amplifier and B port sense amplifier.

Abstract: A first sensor for the detection of dielectric failure (by burning) within a multilayer printed circuit assembly comprises an isolated conductive layer. This first sensor is connected by a first diode to a single wire which also connects a second, temperature, sensor via a second diode (system ground is a return). A number, nominally 16, of such single wire connected sensor pairs are selectable in accordance with an externally (microprocessor) furnished address. During a first time period, an externally (microprocessor) selected interrogation of temperature causes a first, positive, voltage bias to be applied to the selected sensor pair resulting in a current linear with temperature (over the range of 0.degree. C. to 100.degree. C.) in the second sensor. This current is transformed to voltage, offset by 273.degree. Kelvin, amplified, and converted to a digital value for issuance to an external (microprocessor) requestor.

Abstract: A cyclical machine forming tool utilizes positionally justified form knives so that, nominally, a selected 80 out of 120 total stripped wire ends of flat ribbon cable may be selectively simultaneously formed, for bent, into a contour such as is useful for soldered attachement to printed circuit cards. Positional justification of wire-forming hammer elements called form knives, nominally 41 in number, across a variable distance, nominally 1.676.+-.0.009 inches, is expediently repetitively accurately accomplished by wedging them apart with interspersed counterposed knife elements, nominally 40 in number, called adjuster knives.

Abstract: A biasing network comprising two nominal type GZ 2422D transorbs, two resistors nominal 68 ohms and one resistor nominal 110 ohms replicated at each combined differential current driver of nominal type Am26L531 and differential receiver of nominal type Am26L532, as jointly form a transceiver, which are upon a two-wire differential signal communication path allows communication to transpire at a common-mode offset voltage, nominally .+-.8 volts, which is greater than the differential signal voltage that the receiver does elsewise communicate at, and which common-mode offset voltage is at a level which might but for the biasing network damage or destroy the driver.

Abstract: A first sensor for the detection of dielectric failure (by burning) within a multilayer printed circuit assembly comprises an isolated conductive layer. This first sensor is connected by a first diode to a single wire which also connects a second, temperature, sensor via a second diode (system ground is a return). A multiplicity, nominally 16, of such single wire connected sensor pairs are selectable in accordance with an externally (microprocessor) furnished address. During a first time period, an externally (microprocessor) selected interrogation of temperature causes a first, positive, voltage bias to be applied to the selected sensor pair resulting in a current linear with temperature (over the range of 0.degree. C. to 100.degree. C.) in the second sensor. This current is transformed to voltage, offset by 273.degree. Kelvin, amplified, and converted to a digital value for issuance to an external (microprocessor) requestor.

Abstract: A type of Superconducting Quantum Interference Device (SQUID) requires that relatively large, circular, toroidally wound wire coils within a first cavity of a superconducting canister should be inductively coupled to a relatively small SQUID created as an annular ring plus Josephson junctions upon a substrate within a second cavity of the superconducting canister. The required inductive coupling is through a dielectric filled cavity called a coupling cavity which is conical in the shape of a dunce's cap. The conically shaped coupling cavity within the superconducting canister minimizes the parasitic stray inductance which is coupled to the SQUID, and thusly improves the noise performance of the SQUID.

Abstract: An analog speech signal is sampled of a nominal rate of 6 kilohertz and digitized in a Mu-Law Encoder. The digital output of the Mu-Law Encoder is converted by a microprocessor performing table look-up to linearized pulse code modulation (PCM) samples nominally of eight bits per sample. Using a BSPCM (Block Scaled Pulse Code Modulation) method, in each block of nominally 246 eight-bit PCM samples (representing approximately 41 milliseconds), the maximum and minimum sample values are found and used to calculate a scale factor equal to the maximum sample value minus the minimum sample value, with the difference being then divided by a constant number nominally equaling 16. Then the BSPCM samples are generated from the PCM samples each as a corresponding one PCM sample minus the minimum PCM sample value, the difference being then divided by the scale factor. In effect, the bit rate is reduced by adjusting the step size to follow the local block dynamic range.

Abstract: Apparatus for selectively extracting, magnifying and juxtapositioning selected areas of a raster scan image relative to the primary image so as to permit an observer to better view selected areas of the primary image while still viewing the entire primary image. The apparatus essentially comprises means for sampling x and y radar address data and related video data, means for independently and selectively scaling and offsetting the address data for a primary image memory and for a local zoom memory and means for selecting the areas of the primary image that are to be magnified. The selected areas of the primary image are displayed at a rate defined by a zoom magnification factor, scaled and offset independent of the primary image--but relative to the local zoom area, and displayed by extracting the data from the local zoom memory, rather than the primary image memory, as the display raster scans the areas of the screen where the zoom image is to be displayed.

Abstract: A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate 1/2, constraint length 7 code with generator polynomials x.sup.6 +x.sup.5 +x.sup.3 +x.sup.2 +1, and x.sup.6 +x.sup.3 +x.sup.2 +x+1. The architecture of the instant decoder is appropriate for implementation on a single, monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input symbol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output signals of which are evaluated by a majority vote circuit which produces data output signals representative of data input signals.

Abstract: The loading (writing) of plural successive data strings of specifiable bit-length and numbers to a scan/set testable register (called a CONTROL STORE SCAN LOOP STRING) from which it may then be transferred to a control store (called a CONTROL STORE (RAM)) both within a remote slave digital logic device (called a CENTRAL COMPLEX) is bit-serially conducted upon one signal line of a scan/set network by a controlling digital logic device (called a SUPPORT PROCESSOR) in substantially simultaneous time to the reading of the previous contents of such register (and control store) bit-serially via another signal line of said scan/set network. Both signal lines and devices together form a circular BIT-SERIAL SCAN LOOP, upon which the bit-serial writing and reading is time overlapped.

Abstract: A superconducting quantum interference device (SQUID) is direct current biased through physical connections asymmetric to, and preferably maximally asymmetric to, the two Josephson junctions. The asymmetric SQUID so created is, responsively to such physical asymmetry, biased for operation in the linear region of the input magnetic flux/output (voltage or current) device response curve. A resistance of specified value is connected in parallel, or shunt, to the parasitic bridge capacitance of the asymmetric SQUID in order to minimize hysteresis. Two asymmetric SQUIDS of opposite asymmetry are serially connected as a push-pull linear amplifier stage which exhibits zero output (voltage or current) at zero input magnetic flux, and which is specifiable in parameters of construction so as to exhibit optimum linearity of response about such point.

Abstract: A method of and apparatus for encoding computer program instructions and data greatly reduces the total storage requirements. Upon compiling each computer program segment, statistics are generated regarding the frequency of use of each unique program operator and each unique program operand. The operators and operands are encoded using the information theoretic encoding technique. A conversion table is also prepared which enables the object computer to translate the encoded operands and operators during that time when the computer program segment is being executed. Apparatus within the object computer decodes the encoded operands and operators using the conversion tables enabling execution of the computer program segment.

Abstract: A method and apparatus for pseudorandomly decrementing the intensity of data that is displayed on a raster scan display screen. The apparatus essentially comprises means for selecting and partially decrementing data from an image memory and means for controlling the rate at which the partially decremented data is written back into the image memory so that an apparently uniform phosphor decay rate is observed by a viewer.

Abstract: A high speed data base search system which contains a general purpose computer coupled to a special purpose processor called the High Speed Search Function or HSSF. The HSSF may be external to the computer having a standard Input/Output communication path. An alternative approach places the HSSF internal to the computer providing communication via an internal bus. The HSSF is identical in either configuration except for the interface logic. The HSSF is programmable by the computer to perform complex searches on variable size data bases. The internal memory of the HSSF is loaded with the data base to be searched. Registers within the HSSF are loaded with reference words which define the search bounds. The field format register of the HSSF is loaded with a definition of the data base. The field comparison register is loaded to define the field-by-field search criteria. The Boolean Expression loaded into the HSSF defines which compare results are to be considered a hit.

Abstract: A first sensor for the detection of dielectric failure (by burning) within a multilayer printed circuit assembly comprises an isolated conductive layer. This first sensor is connected by a first diode to a single wire which also connects a second, temperature, sensor via a second diode (system ground is a return). A multiplicity, nominally 16, of such single wire connected sensor pairs are selectable in accordance with an externally (microprocessor) furnished address. During a first time period, an externally (microprocessor) selected interrogation of temperature causes a first, positive, voltage bias to be applied to the selected sensor pair resulting in a current linear with temperature (over the range of 0.degree. C. to 100.degree. C.) in the second sensor. This current is transformed to voltage, offset by 273.degree. Kelvin, amplified, and converted to a digital value for issuance to an external (microprocessor) requestor.

Abstract: Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.

Abstract: An N bit input word is partitioned into parts, preferably N/3 parts of 3 bits each. Each part is counted in parallel for the number of binary ones contained therein in first stage parallel code generators, preferably in N/3 parallel berger code generators each producing on 2 binary encoded signal lines that number of binary ones as are contained within 3 input signal lines. The binary encoded signal lines from the parallel code generators are added in a second stage binary tree of adders, such adders as are used in conjunction with first stage berger code generators progressing from N/6 adders of 2 bits width at level 1 to 1 adder of ln.sub.2 (N/3)+1 bits width at level ln.sub.2 (N/3). The final adder produces (X+1) binary encoded signals representing the number of binary ones contained within the input word, 2.sup.X+1.gtoreq. N.

Abstract: A first feedback loop to a regulator transistor within the drain circuit of the input field effect transistor (FET) serves to maintain the voltage across the drain-gate junction of the input FET at a constant value consistent with FET operation as a source follower, thereby mitigating junction to junction capacitances within the FET. A second feedback loop created guard circuits on the cases of the input FET and the drain circuit regulator transistor, thereby mitigating junction to external circuitry capacitances. A third feedback loop modifies essentially constant current flow in the source circuit of the input FET in order to compensate for capacitance within that circuit. When utilized in compact form for microprobing of low voltage nanosecond rise time signals, the amplifier demonstrates an effective input capacitance of less than 0.5 picofarads.

Abstract: Direct current inrush upon connection of a capacitive load to a d.c. voltage is limited through an intermediary circuit. Within such circuit the inrush current is sensed by a series resistance and such sensing is utilized via a feedback loop, to control a series current regulating transistor to be cyclically conducting or non-conducting of a first direct current path. A second direct current path through freewheeling diodes flows current to the load only when such series current regulating transistor is non-conducting of such first path current. After fully charging the capacitive load, howsoever slowly as desired, the first current path conducts with low power dissipation while the second current path is non-conducting. The circuit is further controlled to be correctly operative for control of inrush current during the turn-on, or disruption of, fundamental power to such circuit.

Abstract: A data word of less than or equal to 2.sup.N bits is counted for the number of binary "1's" contained therein in log.sub.2 2.sup.N =N cycles of 3 steps each in a microprocessor. As a first step the data in a first register is logically ANDed in an arithmetic logic unit (ALU) with a mask constant from a first read only memory (ROM), with a first logical product result placed in a second register. As a second step the data from the first register is logically ANDed in the ALU with the same mask constant complemented, and a second logical product result is placed in the first register. Meanwhile, the first logical product result in the second register is shifted in a shift matrix in accordance with a shift count constant obtained from a second ROM. As a third step the shifted first logical product result from the shift matrix is ADDed in the ALU with the second logical product result from the first register, and a sum result is placed in the first register as data.