Abstract: A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.

Abstract: Electrical detection is provided for dicing damage to moisture barrier/edge seals of IC chips which include a low-K dielectric material, a moisture barrier/edge seal for the IC chip, and a moisture damage sensor circuit positioned on the IC chip in proximity to the moisture barrier/edge seal. One or a plurality of moisture barrier/edge seals can be positioned along peripheral edges of the IC chip, and one or more moisture damage sensor circuit(s) can be positioned between the plurality of moisture barrier/edge seal(s), or between an active area of the IC chip and the moisture barrier/edge seal(s), or on a peripheral area of the IC chip outside of the moisture barrier/edge seal(s).

Abstract: A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.

Abstract: A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.

Abstract: A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.

Abstract: A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.

Abstract: A structure having a p-n junction in a semiconductor having a first p-type region and a first n-type region along with a region located in the vicinity of the p-n junction that is doped with a rare-earth element. In addition, the structure includes a charge source coupled to one of the p-type region and n-type region for providing charge carriers to excite atoms of the rare-earth element. Also provided is a method for producing the structure that includes providing a bipolar junction transistor; doping a region in a collector of the transistor with a rare-earth element; and biasing the transistor to generate light emission from the rare-earth element doped region.

Abstract: A method and structure tests devices on a wafer by applying an electrical bias to the devices and simultaneously monitoring emitted light from all of the devices. The emitted light indicates locations of defective devices and records time-based images of the emitted light across the wafer.

Abstract: An integrated ferroelectric/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, where the electrodes do not decompose at deposition or annealing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer being a metal oxide which at least partially decomposes during deposition and/or subsequent processing is provided as well as a method of fabricating the same.

Abstract: A mask/wafer control structure and an algorithm for placement thereof provide for data placement of measurement control structures, called a PLS, Process limiting Structure, on a mask and a plurality of chips on the wafer which provide for tighter control of both mask manufacture and wafer production by providing the most critical design structures for measurement during creation of the mask, and in the photolithography and etch processes. The PLS structures are located at multiple locations throughout the chip, and so they receive the same data preparation as the chip, and measurement tools are able to measure the same features at each fabrication step from fabrication of the mask to final formation of the etched features. Manufacturing control and the interlock between the wafer fabrication and the mask fabrication are enhanced, allowing for improved quality of the final product.

Abstract: A method of ensuring against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 Å, serves a sacrificial purpose and prevents interaction between any fluorine that is released during the refractory material deposition step from interacting with the underlying silicide.

Abstract: A method for forming for inhibiting the buildup of cerlum-containing deposits in a process tool is disclosed. The method involves spraying a solution of a dilute acid, preferably nitric or perchloric acid, through the chamber and bowl rinse nozzles of the process tool. The method is less time consuming than previous methods for inhibiting the buildup of cerium-containing deposits and can be conveniently carried out at the end of every shift.

Abstract: A trough adjusted optical proximity correction for vias which takes into account the topography on a wafer created by prior processing. The vias are classified into one of two groups, coincident vias which have an edge coincident with an edge of the trough, and noncoincident vias which do not have an edge coincident with an edge of the trough, by analyzing the via and trough designs. Any coincident via is marked as valid for an optical proximity correction (OPC). Any noncoincident via is marked invalid for OPC. OPC is then performed to the via level. Only vias marked as valid for OPC will keep the correction. All other vias will keep their original design size. Alternatively, coincident vias can be simply treated differently from noncoincident vias. For instance, coincident vias can be subjected to an aggressive OPC correction, while noncoincident vias are subjected to a less aggressive OPC correction.

Abstract: A capacitor structure formed on an insulation layer includes a lower electrode formed on a surface of the insulation layer, a dielectric layer formed on a surface of the lower electrode, an upper electrode formed on a surface of the dielectric layer, a first spacer formed on a side portion of the upper electrode, and a second spacer formed on a side portion of the first spacer and a side portion of the lower electrode. This capacitor structure is formed by depositing a metal-insulator-metal capacitor stack on top of a via, masking and etching an upper electrode of the metal-insulator-metal capacitor stack, depositing and etching a first spacer on an edge surface of the upper electrode, defining a lower electrode of the metal-insulator-metal capacitor based on the first spacer, depositing and etching a second spacer on a surface of the first spacer and an edge of the lower electrode, and forming a wiring layer on a surface of the upper electrode and a surface of the second spacer.

Abstract: A system and method of monitoring and predicting tool overlay settings comprise generating current lot information, generating historical data, categorizing (binning) the historical data into discrete exposure field size ranges, and predicting current lot tool overlay settings based on the current lot information and historical data. The method monitors the overlay errors during each lot pass through each lithographic process operation. Moreover, the method uses a feedback sorting criteria to monitor the tool overlay settings. Furthermore, the current lot information comprises lithographic field dimensions, wherein the lithographic field optics distortion data is derived from the current lithographic process tool. Additionally, the historical data comprises same-bin lithographic field size dimensions of previous lots, which statistically means the data is derived from the same (or similar) bin of like lots, on the current lithographic process tool.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: A method and system for determining overlay tolerances. The method comprises the steps of exposing wafers at different critical dimensions (preferably, above, below, and at optimum image size); and varying the overlay across each wafer, preferably by intentionally increasing the magnification. Functional yield data are used to determine the overlay tolerance for each of the image sizes. The present invention, thus, studies the interaction of image size and feature misalignment. Prior to this invention, the only way to attain this information was to process a large number of lots and create a trend of image size and alignment vs. yield. The present invention solves the problem by determining the overlay tolerance based on yield data from a single lot. The design can then be altered or the overlay limit can be tightened (or relaxed) based on failure analysis of the regions/features that are most sensitive to misalignment.

Abstract: A method of providing a substantially planar trench isolation region having substantially rounded corners, said method comprising the steps of: (a) forming a film stack on a surface of a substrate, said film stack comprising an oxide layer, a polysilicon layer and a nitride layer; (b) patterning said film stack to form at least one trench within said substrate, wherein said patterning exposes sidewalls of said oxide layer, polysilicon layer and nitride layer; (c) oxidizing the at least one trench and said exposed sidewalls of said oxide layer and said polysilicon layer so as to thermally grow a conformal oxide layer in said trench and on said exposed sidewalls of said oxide layer and said polysilicon layer; (d) filling said trench with a trench dielectric material; and (e) planarizing to said surface of said substrate.