Abstract: A technique for reducing element disable fuse pitch requirements in an integrated circuit device incorporating replaceable elements wherein each group of replaceable elements contains a circuit which enables an element group within a chained set to determine whether it is the "leftmost" (or first) element used within the set by monitoring the state of an adjacent node. The node will transition to a logic "low" level if (and only if) a fuse within the set, (and located to the left of the node) is "blown" (or opened). By then multiplexing signals to select one or more elements within the first group and additional signals to select one or more elements within the second group, the necessary determination can be made to disable any given pair of elements based on the state of the fuses, the adjacent nodes and the additional signals.

Abstract: A system of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services is placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

Abstract: A word line boost-on-writes technique for a dynamic random access memory device in which the word lines are initially boosted upon opening of a page in the memory array and then again following each write command, or following a predetermined number of write cycles in the case of a burst write, in order that the precharge cycle can proceed without delay due to the boost operation. Each boost is applied for a limited duration so that the overall precharge time is not affected.

Abstract: A method for operating a processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

Abstract: A low static enclosure has an interior for holding an electronic device therein. The electronic device has opposing walls each having a guide rail thereon. The enclosure has a bottom, a top, and a backplane between the bottom and top at their respective back edges. The backplane has an electric connector on its interior surface. The bottom and top each have a flat continuous interior facing surface with a groove extending from the front edge to the back edge. The grooves on the bottom and top are for cooperation with the guide rails on the opposing walls of the electronic device to slide the electronic device along the bottom and top respectively so that an electric connector on the electronic device mates with the electric connector on the interior surface of the backplane. The flat continuous interior facing surfaces of the bottom and top discourage ESD between the surfaces and the electronic device.

Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H.sub.2 O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.

Abstract: An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memory devices. The memory device provides a high speed memory access device of particular utility in conjunction with DSP processors with performance equivalent to that of SRAM memory devices but requiring a significantly small die size which allows for the provision of greater effective memory capacity per die area. The internal refresh functionality of the device provides for all refresh operations to the DRAM memory array to occur transparently to the device user and provides control signals alerting the associated controller when refresh operations are being performed.

Abstract: A SCSI bus extender apparatus coupling a primary SCSI bus to a secondary SCSI bus includes a mechanism for detecting and resolving contention between a substantially simultaneous SELECTION operation on the primary bus and a RESELECTION operation on the secondary bus. The inventive method contemplates the bus extender arbitrating for control of the primary bus after a conflict is detected, and releasing control of the secondary bus if control of the primary bus is obtained. A target device on the secondary bus can then rearbitrate for control of the secondary bus. Once the target device controls the secondary bus, it can direct a RESELECTION signal to the bus extender, which responsively directs the signal to an initiator device on the primary bus. If the bus extender is unable to gain control of the primary bus after a conflict is detected, the SELECTION operation is allowed to proceed and the target device reattempts to assert the RESELECTION operation thereafter.

Abstract: Fees due from transactions in electronic commerce are processed by building a transaction information database with transaction event objects based on events in each transaction. After retrieving fee rules from a fee rule database, a determining step detects if the fee rule applies to information in a transaction event object. Then, if the fee rule applies, a calculating step calculates the fee based on the fee rule and the information in the transaction event object. A fee object for a recipient entity is created based on the fee calculated by said calculating step and is stored in a payment database. An accumulating step sums the payments for a recipient entity from the fee objects in the payment database. The fee rules are general fee rules and specific fee rules. The general fee rules are applied to information in a transaction event object, and a calculating step calculates a general fee based on the general fee rule and the information in the transaction event object.

Abstract: The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache.

Abstract: A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe.

Abstract: An efficient method for purging cache memory sub-blocks within a cache memory block is disclosed. The method is particularly applicable to cache memories established on rotating magnetic media, such as a hard disk drive. The method is unique in that it requires absolutely no system overhead when the system is running and the cache is not completely full. When all sub-blocks within the cache memory have been filled, sophisticated, system resource-intensive algorithms are not employed to determine which is the oldest or the least frequently used sub-block of data. Instead, sub-blocks of data are removed in a pseudo-random manner until ample space is available within the cache.

Abstract: An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.

Abstract: In a computing system having a plurality of storage devices, notification of an application program of a change of state in a storage device so that corrective action can be taken. A notification module creates and maintains an event queue for storing events corresponding to changes in the state of the storage devices. The notification module indicates to the application programs that events are in the queue. The queue conditions are monitored by the notification for queue maintenance.

Abstract: A method for verifying a desired operation of an untrusted memory device is performed under load and includes shadowing read and write operations to the untrusted memory device and to a trusted memory device. The shadowing is performed by concurrently writing data to both the trusted and untrusted memory devices, and concurrently reading data from both the trusted and the untrusted memory devices. All data returned from the trusted and untrusted memory devices in response to the read operations are compared, and if any data compared does not have a same value, a value from the trusted memory device is returned and an error indication is generated.

Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

Abstract: A dynamic set/reset circuit is provided with a first feedback line and a second feedback line. The first feedback line provides an interlocked feedback signal which permits high frequency operation of the set/reset circuit. The second feedback line prevents the interlocked feedback signal from causing the circuit to improperly change state until the next cycle of the circuit. In this manner, the circuit will operate properly despite an unexpectedly wide pulse on an input line. The dual feedback can be used on the set or reset inputs of a set/reset circuit, or both, and the set/reset circuit can be used in various logic and high speed applications, such as within a microprocessor.

Abstract: In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to physical addresses. The processor has a register window movable within a register file, a window pointer register maintaining a value corresponding to the location of the window in the register file, a speculative window pointer register maintaining a speculative value of the window pointer register. A controller identifies an instruction expected to modify the value in the window pointer register, and in response to identifying the instruction the controller modifies the speculative value. A mapper, coupled to the speculative window pointer register, converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.

Abstract: In a SCSI subsystem having mixed wide and narrow SCSI devices installed, a method and apparatus is provided for detecting a narrow SCSI device illegally installed at a slot assigned to a wide SCSI device. To detect the narrow SCSI device installed at an illegal location, high ID and low ID SCSI bus address pairs are set as test pairs for the SCSI subsystem. The low ID is the alias of the high ID if a narrow SCSI device is installed at the high ID slot. To detect a conflict with a controller ID, a non-responsive ID bus address corresponding to a slot known to be unused is called. A response to this call indicates a narrow SCSI device is installed at the high ID of the test pair and the narrow SCSI device at the high ID has configured to an alias bus address matching the controller ID. To detect a present conflict between SCSI devices, the low ID bus address in the test pair is called.

Abstract: A system, method and computer program product which determines the relative performance of a local cache and renders the resultant performance increase (or in certain circumstances, the decrease) in cache performance of a stand-alone computer or networked "client" perceptible to the user in an especially intuitive manner. By accurately tracking and factoring in the times and amounts of data read from one or more source locations and the cache, the amount of time required to execute "read" operations without the cache can be determined. By dividing this time period by the actual time to execute the "read", the true relative performance of the cache may be determined.