Abstract: An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform the testing. The interface allows for the verification of an embedded memory macro design utilizing a test interface which includes the memory macro and separate on-chip test circuitry so that half-rate, narrow word, input signals from a tester can perform all memory macro operations across the breadth of a wide memory macro input/output (“I/O”) architecture. The on-chip test circuitry may also include a synchronizing circuit to minimize skew between the external clock and the data output from the test chip.

Abstract: A time data compression technique which allows high speed integrated circuit (“IC”) memory devices to be tested at full speed with test equipment which is capable of operating at only at relatively slower speeds than that of the memory devices without increasing test time or decreasing production throughput. Through the use of the technique disclosed herein, data is initially sorted in time and them compared for a predetermined number of logic level “1s” or “0s” to be effectively compressed in time. This time compression allows high rate data streams to be tested at effectively slower rates. The technique of the present invention can be utilized to effectively reduce the data rate by one half, one quarter or to any sub-multiple of the normal memory frequency without increasing time in test.

Abstract: A method of storing and accessing two data bits in a single ferroelectric FET includes selectively polarizing two distinct ferroelectric regions in the same gate dielectric layer separated by a non-ferroelectric dielectric region. A first ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the source and is polarized in one of two states to form a first data bit within the FET. A second ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the drain and is polarized in one of two states to form a second data bit within the FET. Detection of the first data bit is accomplished by selectively applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages.

Abstract: A system and method for a computer file system that is based and organized upon hashes and/or strings of digits of certain, different, or changing lengths and which is capable of eliminating or screening redundant copies of aggregate blocks of data (or parts of data blocks) from the system. The hash file system of the present invention utilizes hash values for computer files or file pieces which may be produced by a checksum generating program, engine or algorithm such as industry standard MD4, MD5, SHA or SHA-1 algorithms. Alternatively, the hash values may be generated by a checksum program, engine, algorithm or other means that produces an effectively unique hash value for a block of data of indeterminate size based upon a non-linear probablistic mathematical algorithm.

Abstract: A multi-mode motor controller architecture includes a motor, an integrated circuit controller, and an integrated circuit driver circuit. The integrated circuit controller includes a pulse generator, a DAC, an ADC, and a digital compensator circuit. The integrated circuit driver circuit is in communication with the controller and includes an error amplifier, first and second output amplifiers for driving the motor, and a sense amplifier. The motor controller architecture is configurable to operate in a linear mode, a pulsed mode, or a switchable linear/pulsed mode. The controller architecture can be implemented with external compensation circuitry, such as a resistor-capacitor circuit, or with the digital compensation circuitry located within the controller integrated circuit.

Abstract: A pipelined arbitration mechanism allows a routing control decision to be effected for a later packet while a current packet is being transferred. The later packet can be issued a fixed number of cycles after the current request. The mechanism has particular advantages when used with a plurality of functional modules connected to a packet router, whereby a single functional module can generate a current request relating to a current packet and a deferred arbitration request relating to a later packet to be issued a fixed number of cycles after the current request.

Abstract: A system and method for availability management coordinates operational states of components to implement a desired redundancy model within a high-availability computing system. Within the availability management system, an availability manager monitors various reports on the status of components and nodes within the system. The availability manager uses these reports to direct components to change states if necessary, in order to maintain the desired system redundancy model. The availability management system includes a health monitor for performing component status audits upon individual components and reporting component status changes. The system also includes a watch-dog timer, which monitors the health monitor and reboots the entire node containing the health monitor if it becomes non-responsive. Each node within the system also includes a cluster membership monitor, which monitors nodes becoming non-responsive and reports node non-responsive errors.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract: A compact speed measurement system for field or onsite use in measuring speeds of vehicles and capturing images of select vehicles. The system includes a laser speed detector for determining a speed of a vehicle in a specific target area. When a speed is determined, the detector generates a speed signal. The system includes a camera generally aligned with the speed detector operable to capture and store digital still images of vehicles in memory. The camera is programmed to respond to an image capture signal to generate and transmit a digital image file including a still image of the vehicle targeted by the detector. A portable field processor is communicatively linked to the speed detector and the camera to first receive the speed signal, to process the speed signal and to transmit an image capture signal to the camera, and to receive the digital image file from the camera.

Abstract: The present invention provides an automated problem identification system. The invention analyzes a customer's computing environment, including administration practices, system configuration including hardware, software and the operating system. Then the invention compares the computing environment to an internal rules database. The internal rules database is a compilation of various problems that are known to exist on various configurations. Then, instead of calling an expert when there is a problem and repeating the process for every customer, the invention uses a proactive approach by analyzing a given system configuration and comparing it to a body of known problems, before the system breaks down.

Abstract: A single transistor (“1T”) ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric. The memory cell of the present invention comprises a substrate, an overlying ferroelectric layer, which may comprise a film of rare earth manganite, and an interfacial oxide layer intermediate the substrate and the ferroelectric layer. In a preferred embodiment, the ferroelectric material utilized in an implementation of the present invention may be deposited by metallorganic chemical vapor deposition (“MOCVD”) or other techniques and exhibits a low relative dielectric permittivity of around 10 and forms an interfacial layer with a relative dielectric permittivity larger than that of SiO2, which makes it particularly suitable for a 1T cell.

Abstract: A refresh initiated precharge technique using look-ahead refresh eliminates the need to close banks in a dynamic random access memory (“DRAM”) array prior to executing a “refresh” command by taking advantage of the fact that the actual initiation of an internal “refresh” operation is delayed by at least one clock cycle from the execution of the external “refresh” command. The technique is effectuated through the issuance of a “refresh” command to cause all banks within the DRAM array to precharge. This precharge occurs prior to the n-cycle delay (where N=1 or more clock cycles) of the internal “refresh” operation.

Abstract: A digital data separator that is capable of separating data signals and clock signals from an encoded data stream. The digital data separator includes a synchronizer to synchronize the encoded data stream with the system clock of the digital data separator. An up-counter counts the number of clock pulses between valid logic 1's in the encoded digital data stream. Combination logic compares the value of the up-counter with established threshold values to determine whether the data separator has received a valid logic 1. The combinatorial logic also reset the up-counter on determining that a valid logic 1 was received.

Abstract: A method for automatically determining whether a browser supports scalable vector graphics (“SVG”). The method uses a two prong process to make a proper detection for various types of browsers. The method includes using JavaScript to detect Multipurpose Internet Mail Extensions (“MIME”) types from the browser to detect SVG support. If scanning of the MIME types detects that SVG support is present, the requested web page containing SVG content is sent. If no SVG support is detected, the non-SVG version of the web page is sent to the browser. If the browser does not return a list of MIME types, the method of Visual Basic Scripting Edition language (“VBScript”) to instruct the browser to create an SVG object on the client device. If the object is created, SVG support has been detected, and the browser is served the web page having SVG content.

Abstract: A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

Abstract: A computer network has a subnetwork of computers including a server, a first authentication server, a firewall, and network interconnect. This subnetwork is connected through encrypted protocol handlers and over a potentially insecure channel to a second authentication server. Some authentication requests, especially for users not authenticated in the first authentication server's database and determined by the first authentication server to be authenticatable by the second authentication server, are passed from the server of the subnetwork through the encrypted protocol handlers and over the potentially insecure channel to the second authentication server.

Abstract: A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2× frequency clock from the 1× frequency external clock signals (two 1× clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.

Abstract: A caching pattern and associated method for caching in a programming environment are disclosed. The caching pattern includes an extensible cache entry component that includes methods for retrieving, updating, and setting expiration parameters for a cache entry. A cache store component includes methods for reading and writing objects to cache entries. A cache manager component includes methods implementing a first interface to the cache store component to cause the cache store component to read and write objects to the data store and includes methods implementing a second interface to the cache entry component for adding, removing, getting and committing data to the cache entry. The cache store component may also include instantiating a virtual machine and the caching pattern may be used, in one embodiment, in a JAVA programming environment.

Abstract: A technique for maintaining referential integrity between data records in any data architecture in which only a single copy is kept of any particular data record. The technique includes providing the ability to bind a data record to a parent data record by storing the data record in a manner associated with the parent record. If the data record then is bound to other parent data records, a link reference is used that is stored in an attribute of the data record, rather than associating another copy of the data record with the second parent data record. It is possible to bind any data record to any other data record, so circular relationships can be created. In addition, there are special methods used when a data record is to be deleted to make sure that all parents or children of that data record are considered, in order to update bind information or delete the children as may be appropriate.

Abstract: A simultaneous function dynamic random access memory (“DRAM”) technique of particular applicability to DRAMs, synchronous DRAMs (“SDRAM”), specialty DRAMs, embedded DRAMs, embedded SDRAMs and the like which enables the execution of “read”, “write”, “active” and “precharge” commands on a single clock cycle. The technique of the present invention is of especial applicability to embedded memory arrays or specialty DRAMs where the number of input signals to the DRAM are not necessarily limited by mechanical component packaging constraints or component pin counts. In general, the advantages of the technique are obtained through the use of separate address fields, including bank addresses, for “read” and “write” commands, and separate bank addresses for “active” and “precharge” commands with a resultant highly parallel operational functionality.