Abstract: An apparatus and method for canceling an echo signal is disclosed. The apparatus includes an echo filter, an up-sampler, an interpolation filter, and a signal combining apparatus. The echo filter filters the transmitted signal, the up-sampler up-samples the output of the echo filter, the interpolation filter filters the up-sampled output to generate a signal that emulates the echo signal, and the signal combining apparatus combines the signal emulating the echo signal with the received signal to remove echo signal. The method estimates an impulse response of the echo channel for estimation of filter coefficients of an echo filter. The transmit signal is then filtered in the echo filter to generate an output, which is up-sampled to generate another output. The up-sampled output is filtered by the interpolation filter to generate a signal that emulates the echo signal, which is then combined with the received signal to cancel the echo signal.

Abstract: A method and system for generating prime numbers and testing for primality of an integer. This invention has applicability to “public key” and other encryption techniques that play an important role in the security of information technology and electronic commerce. Generation of prime numbers requires the step of testing the pnmality. The method includes a deterministic test for testing the primality of a number in polynomial time. The system includes a random number generator and a primality tester. The random number generator generates a random number and the primality tester tests the primality of this random number. The primality tester can also be used independent of the random number generator. In such a case, the number whose primality is to be tested can be input via a user interface.

Abstract: A system and method for enforcing policies on data packets in a computer network is disclosed. The enforcement of policies is done by prioritizing and regulating the flow of data packets. The regulation of prioritized data packets includes a determination of: service level agreement violations, flow control of data packets of a predefined priority and session resettings. For determination of service level agreements the policy engine carries out a response time calculation and finds if it is in consonance with the response time agreed upon in the service level agreement. Flow control in case of a service level agreement violation is implemented either by reducing the server side window size or by delaying acknowledgement packets sent by the client.

Abstract: The disclosed invention provides a system, a method and a computer program product for timing offset estimation for frequency selective fading channels in wireless communication systems. The disclosed invention first obtains a corrected received signal using the received signal and a pre-estimated timing offset. The pre-estimated timing offset is further tracked in two steps. In the first step a plurality of probable deviations in the pre-estimated timing offset are considered. Then a training sequence is used to determine an expected signal corresponding to each of the probable deviations. The corrected received signal is then shifted through the probable deviations. Thereafter error factor between the expected signals and corresponding shifted received signals is obtained. The probable deviation yielding optimum error factor is then identified as the first estimate of the deviation in timing offset.

Abstract: A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, it is converted to a fixed delay circuit by using additional circuitry to obtain a fixed delay circuit. If the fixed delay circuit is a logic circuit that performs multiple cycle computations, it is converted to a logic circuit that performs the same computation in a single cycle. Circuit acceleration includes concatenating multiple copies of the fixed delay circuit. After performing circuit acceleration on all sub-circuits in the fixed delay circuit, a combined accelerated circuit is obtained. Thereafter, redundant flip-flops are identified and removed from the combined accelerated circuit and the combined accelerated circuit is optimized.

Abstract: A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot associated with an object is a function of time, and it represents the functionality of the element at a given time. The method comprises the steps of determining a phase-list, determining ticks associated with each object of the circuit. Based on these ticks, slots are generated. Further, relations between the slots of the various objects of the circuit are captured.

Abstract: A photonic structure for “white” light generation by phosphors under the excitation of a LED. The photonic structure mounts the LED and an optically transparent nanocomposite matrix having dispersed therein phosphors which will emit light under the excitation of the radiation of the LED. The phosphors dispersed in the matrix may be nanocrystalline, or larger sized with the addition of non light emitting, non light scattering nanoparticles dispersed within the matrix material so as to match the index of refraction of the matrix material to that of the phosphors. The nanocomposite matrix material may be readily formed by molding and formed into a variety of shapes including lenses for focusing the emitted light. A large number of the photonic structures may be arranged on a substrate to provide even illumination or other purposes.

Abstract: A system, method and computer program product for detecting a frequency burst in a received signal at a wireless receiver is disclosed. The invention predicts the current sample of the received signal by filtering the past samples of the received signal through an adaptive filter. A prediction error is further obtained by subtracting the actual current sample and the predicted current sample. The prediction error is then used to adapt the adaptive filter. Since the frequency burst is a substantially predictable signal, the adaptive filter adapts to accurately predict the samples of the frequency burst. Therefore, the prediction error decreases when the frequency burst is received at the receiver. The end of the frequency burst is identified using the prediction error at each discrete time instant.

Abstract: A power amplifier with a multi-mode digital bias control circuit is provided. The power amplifier utilizes a complementary reference voltage generation circuit and a bias current-control circuit to generate a plurality of bias current levels for different output power levels. In an embodiment of the present invention, the power amplifier circuit is connected to a reference voltage and two control signals. Depending on the desired output power level, the control signals set the corresponding bias current in the amplifying transistors, to ensure sufficient linearity. The power amplifier is capable of operating at a very low quiescent current level, for example, 5 mA. As a result, a significant improvement in the power amplifier's overall efficiency is achieved, and the battery talk time of a wireless communication device is increased. The invention finds application in wireless communication devices such as CDMA, WCDMA, EDGE and WLAN mobile devices.

Abstract: A method and apparatus for multi-path channel characterization in a Direct Sequence Spread Spectrum based wireless communication system is provided. The multipath channel is modeled as a tapped delay line FIR filter with L taps corresponding to L paths. A pre-defined training sequence is transmitted over the multipath channel. The received signal is sampled and cross correlations are computed between the samples obtained and the spreading sequence for various time lags to obtain the symbol boundary. Thereafter, a desired set of L cross correlations for L time lags around the symbol boundary is estimated. For this, all the L possible sets of L cross correlations for L time lags around the symbol boundary are considered. The energy in the cross correlations corresponding to each considered set is calculated. The set of L cross correlations having the maximum energy is selected for tap computation. The tap coefficients are estimated by solving a set of L simultaneous linear equations.

Abstract: The present invention provides a method and system for clock and carrier recovery in a direct sequence spread spectrum communication system. The process involves the receiver receiving a digital signal that has been transmitted by a remote transmitter. The method for joint clock and carrier recovery comprises the following steps. The received signal is down-converted and the signal is then converted to digital form. The signal is de-spread to obtain the phase of the signal constellation. The clock error at the receiver is then estimated from the phase error of the signal constellation by means of an optimal linear estimator. The discrete carrier frequency offset of the received signal is then estimated from the estimated clock error. The optimal linear estimator used here for estimating the clock error is also the maximum likelihood estimator.

Abstract: The present invention discloses a method and system for computer-aided circuit design for checking the equivalence of data flow graphs by splitting data flow graphs representing finite precision arithmetic circuits into lossless subgraphs representing infinite-precision arithmetic circuits, and edges with information loss. The set of lossless subgraphs generated are leveled, and checked for equivalence as expressions. The edges with information loss are compared by establishing the equivalence of their bit width. The present invention declares data flow graphs as equal, if the respective lossless subgraphs and the bit-width at the corresponding edges with information loss are equal.

Abstract: A method, system and computer program product for obtaining the reliability values for the hard decisions obtained by a Viterbi equalizer in a wireless communication system. A difference parameter is obtained for each Viterbi state at a stage while advancing the Viterbi trellis by the stage. The difference parameter for a Viterbi state at a stage is obtained by subtracting the path metric of the non-surviving path from the path metric of the surviving path for the Viterbi state at the stage. The difference parameter corresponding to the Viterbi state on the ML path at a stage is used as the reliability value for the hard decision obtained at L stages behind the stage, where L is the memory of the Viterbi trellis. A method for obtaining the accurate reliability values for the hard decisions corresponding to the last L stages of a truncated Viterbi trellis is also provided.

Abstract: The present invention is a system and method for allowing an administrator of a computer network higher up in a hierarchical arrangement to define the scope of policies for the services offered, and users lower in the hierarchical arrangement to customize policies within the scope defined by the administrator. While defining policy rules, administrators classify them as scoping or non-scoping. Users lower in the hierarchical arrangement can then customize scoping rules by defining sub-rules. Policy rules have a condition part and an action part, and the sub-rules can be used to change the scope of the condition and action parts. The present invention adds all the non-scoping policy rules, all the scoping policy rules, and all the sub-rules (with their scope limited by the scoping rules) to a rules database. This rules database is then used by any policy enforcement engine to enforce policy rules.

Abstract: An integrated policy enforcement system for a computer network implements several policies on the network traffic. A rule compiler compiles these policies and converts them into a rule tree-graph, which is then used to provide desired behavior to the network traffic comprising data packets. The rule compiler comprises three sub-modules namely—a rule input module, a rule tree generator module and a rule output module. The rule input module receives the input for the rule compiler and prepares the input for the rule tree generator module. The rule tree generator module generates the rule tree-graph. The rule tree-graph is a data structure comprising tree data structure and graph data structure.

Abstract: The invention provides a system and method that enables a business developer to develop and execute a Wireless Application Gateway (WAG) without programming or writing code. The WAG, as developed and executed through this invention can support a variety of wireless devices and a variety of backend systems. The business developer can, without writing code, configure screens for a plurality of mobile devices and define the business logic to carry out a process involving communication between backend systems and mobile devices. Without the need of programming, the business developer can select and work with a plurality of backend systems and business processes at runtime of the WAG.

Abstract: A method for producing nanostructured multi-component or doped oxide particles and the particles produced therein. The process includes the steps of (i) dissolving salts of cations, which are either dopants or components of the final oxide, in an organic solvent; (ii) adding a dispersion of nanoparticles of a single component oxide to the liquid solution; (iii) heating the liquid solution to facilitate diffusion of cations into the nanoparticles; (iv) separating the solids from the liquid solution; and (v) heat treating the solids either to form the desired crystal structure in case of multi-component oxide or to render the homogeneous distribution of dopant cation in the host oxide structure. The process produces nanocrystalline multi-component or doped oxide nanoparticles with a particle size of 5–500 nm, more preferably 20–100 nm; the collection of particles have an average secondary (or aggregate) particle size is in the range of 25–2000 nm, preferably of less than 500 nm.

Abstract: The present application is directed to the preparation and use of a class of nanoparticles called Quantum Confined Atoms or QCA's. A QCA is a particle of material comprising a plurality of host atoms in a nanoparticle of a size of less than 10 nm with a single atom of a dopant (or activator) confined within. The QCA's have unique luminescent and optical properties and thus can act as a very efficient nanophosphor which generate polarized light and can operate as a laser and a nanomagnet. An anti-agglomeration coating surrounding the nanoparticles can prevent clumping and loss of the enhanced properties.

Abstract: A computationally efficient method and system for decoding shortened cyclic codes is presented. The increase in computational efficiency is achieved by improvement of the syndrome calculation step. Two embodiments of the present invention are described; the first embodiment is optimized for a hardware implementation and the second embodiment is optimized for a Digital Signal Processor (DSP) implementation. The present invention is applicable to decoding of all the binary shortened cyclic codes, including Fire codes used for Coding Scheme-1 (CS-1) for GSM.

Abstract: A rule engine for a computer network traverses a rule mesh having path nodes and path edges in form of a tree part and a graph part. The rule engine evaluates data packets flowing through a network to determine rules matched for every packet. Subsequent packets having same expression values as an already checked packet are not rechecked against the same nodes in the rule mesh through the use of a session entry. The rule engine performs a search on every path node of rule mesh to determine the next path edge to traverse. A Tree-Id and Rule Confirmation Bitmap that are indicative of path traversed and rules matched by a packet are generated at the end of rule mesh traversal. These are appended in the packet extension for subsequent modules of Policy Agent.