Abstract: A plurality of match and priority encoding logic (MPL) circuits are connected in a chain. Each MPL circuit includes a plurality of input terminals coupled to an associated set of match lines from a content addressable memory (CAM) array, an index input port to receive an input index from a previous MPL circuit, an index output port to provide an output index to a next MPL circuit, and a select terminal to receive a select signal.

Abstract: A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, a steering circuit for steering data corresponding to the defective column to the spare column, and a global mask circuit for masking the defective column during a compare operation.

Abstract: A method and apparatus that may be used to disable one or more defective CAM blocks, and to selectively re-assign priority between the remaining enabled CAM blocks. In one embodiment, each CAM block includes an array of CAM cells organized in a number of rows and columns, where each row has a match line to indicate match conditions therein during a compare operation. Each block also includes a block priority encoder coupled to the number of match lines and having an output to provide a row index of a row that stores data that matches comparand data. The row indexes from the CAM blocks are provided to a main priority encoder that stores a dynamic block index for each of the plurality of CAM blocks. The main priority encoder combines each row index with a corresponding block index to generate a device index for each CAM block. The main priority encoder may re-assign priority between the plurality of CAM blocks by manipulating the dynamic block indexes.

Abstract: A CPU includes a register file including a plurality of architectural registers for storing data loaded from a primary memory for execution by the CPU. A stack cache memory coupled to the register file includes a plurality of cache lines, each of which corresponds to one of the architectural registers and implements a first-in, last-out queue for data spilled from the corresponding architectural register. Data spilled from the register file into the stack cache memory is maintained in the stack cache until subsequently restored to the register file without accessing primary memory. The stack cache memory does not participate in cache writeback operations to primary memory.

Abstract: One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

Abstract: An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code.

Abstract: An audio interface is coupled to received a music signal and a microphone signal. The music signal and a volume control signal are combined in a multiplier to produce a volume adjusted music signal. In response to an input signal from a user, the volume control signal is gradually changed in predetermined increment levels. Thus, the multiplier gradually changes the audible volume in these predetermined increment levels. The resulting music and microphone signal are stored in corresponding partitions of a single memory, and thereafter provided to a mixing circuit. The mixing circuit combines signal samples read from the memory to produce four output signals each containing first and second channel samples. The resultant 8 channel samples are gated in a formatter with respective channel mute signals which, when asserted, effectively mute their corresponding channel sample.

Abstract: An audio interface is coupled to received a music signal and a microphone signal. The music signal and a volume control signal are combined in a multiplier to produce a volume adjusted music signal. In response to an input signal from a user, the volume control signal is gradually changed in predetermined increment levels. Thus, the multiplier gradually changes the audible volume in these predetermined increment levels. The resulting music and microphone signal are stored in corresponding partitions of a single memory, and thereafter provided to a mixing circuit. The mixing circuit combines signal samples read from the memory to produce four output signals each containing first and second channel samples. The resultant 8 channel samples are gated in a formatter with respective channel mute signals which, when asserted, effectively mute their corresponding channel sample.

Abstract: A circuit includes a drive transistor coupled between an output and a first potential, a constant current circuit coupled between the gate of the drive transistor and a second potential, and a compensation circuit coupled between the gate of the drive transistor and the first potential. The constant current circuit draws a current from the gate of the drive transistor to the second potential that is substantially independent of process and temperature variations, and therefore turns on the drive transistor at a constant rate, regardless of process and temperature variations. The compensation circuit draws a small current from the gate of the drive transistor to the first potential that is dependent upon process and temperature variations of the drive transistor, and therefore reduces the discharge rate of the gate of the drive transistor according to process and temperature variations of the drive transistor.

Abstract: A monolithic Multi-chip Module (MCM) package includes two or more individual CAM dice mounted on a substrate formed as, for example, a plastic ball grid array (PBGA) package. The substrate includes an interconnect structure to route signals between corresponding pads of the CAM dice and balls of the MCM package. In some embodiments, the footprint of the MCM ball grid array package is identical to the footprint of a similar PBGA package housing a single CAM die. Each CAM die within the MCM package may be assigned the same device identification number (DID).

Abstract: A pre-recorded video of a master's swing motion is stored as first frame sequences in computer memory. Target cues indicative of motion progress are associated with each first frame sequence. A video recording of the student performing the swing motion is stored in computer memory as second frame sequences. Reference cues indicating motion progress of the student are inserted into or associated with each student frame. The first frames are aligned with and normalized to the second frames, and then the first frames are synchronized to corresponding second frames using the target cues and the reference cues. The corresponding first and second frame pairs are superimposed, and immediately thereafter displayed to allow the student to analyze differences between his swing motion and the master's swing motion.

Abstract: A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a primary memory controller to communicate with its primary memory. When there is a cache miss in a CPU, the cache controller routes an address request for primary memory directly to the primary memory via the CPU as a speculative request without access the system bus, and also issues the address request to the system bus to facilitate data coherency. The speculative request is queued in the primary memory controller, which in turn retrieves speculative data from a specified primary memory address. The CPU monitors the system bus for a subsequent transaction that requests the specified data in the primary memory. If the subsequent transaction requesting the specified data is a read transaction that corresponds to the speculative address request, the speculative request is validated and becomes non-speculative.

Abstract: Match lines of a CAM array are grouped into sets and provided to corresponding match and priority encoding logic (MPL) circuits. Each MPL circuit includes an input connected to an output of a previous MPL circuit. The last MPL circuit has an output connected to a control circuit. In response to the set of match signals, each MPL circuit generates a match flag and the index of the highest priority match for the set. In response to the match flags, the control circuit provides a plurality of select signals to corresponding MPL circuits each of which, in response to its select signal, provides either the set index generated therein or a set index received from the previous MPL circuit to the next MPL circuit. The select signals are asserted so that the index of the highest priority match line set ripples through the MPL circuits to the control circuit.

Abstract: A method is disclosed for communicating with an FPGA interface device having a microcontroller when the on-board microcontroller is not responsive to commands from a host system. If the host system determines that the microcontroller is not responsive to commands, the host system sends a null character to the interface device at a predetermined baud rate which is significantly distinguishable from baud rates normally used for communicating with the microcontroller. A logic circuit on the interface device monitors the baud rate of incoming data, and if a null character at the predetermined baud rate is detected, the logic circuit toggles the reset pin of the microcontroller. In response thereto, the microcontroller re-boots itself, and is thereafter able to communicate with the host system. Additional commands are provided to the interface device by using other baud rates which are significantly distinguishable from the baud rates normally used.

Abstract: The main cache of a processor in a multiprocessor computing system is coupled to receive writeback data during writeback operations. In one embodiment, during writeback operations, e.g., for a cache miss, dirty data in the main cache is merged with modified data from an associated write cache, and the resultant writeback data line is loaded into a writeback buffer. The writeback data is also written back into the main cache, and is maintained in the main cache until replaced by new data. Subsequent requests (i.e., snoops) for the data are then serviced from the main cache, rather than from the writeback buffer. In some embodiments, further modifications of the writeback data in the main cache are prevented. The writeback data line in the main cache remains valid until read data for the cache miss is returned, thereby ensuring that the read address reaches the system interface for proper bus ordering before the writeback line is lost.

Abstract: An audio interface is coupled to received a music signal and a microphone signal. The music signal and a volume control signal are combined in a multiplier to produce a volume adjusted music signal. In response to an input signal from a user, the volume control signal is gradually changed in predetermined increment levels. Thus, the multiplier gradually changes the audible volume in these predetermined increment levels. The resulting music and microphone signal are stored in corresponding partitions of a single memory, and thereafter provided to a mixing circuit. The mixing circuit combines signal samples read from the memory to produce four output signals each containing first and second channel samples. The resultant 8 channel samples are gated in a formatter with respective channel mute signals which, when asserted, effectively mute their corresponding channel sample.

Abstract: Where it is desired to perform a double precision operation using single precision operands, first and second single precision operands are loaded into first and second respective rows of a re-order buffer, and third and fourth single precision operands are loaded into third and fourth respective rows of the re-order buffer. A first merge instruction copies the first and second single precision operands from respective first and second rows of the re-order buffer into first and second portions of a fifth row of the re-order buffer, thereby concatenating the first and second single precision operands to represent a first double precision operand. A second merge instruction copies the third and fourth single precision operands from respective third and fourth rows of the re-order buffer into first and second portions of a sixth row of the re-order buffer, thereby concatenating the third and fourth single precision operands to represent a second double precision operand.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a block select circuit. In one embodiment, each CAM block includes a main CAM array having a plurality of rows of CAM cells each coupled to a corresponding word line, and a spare row of CAM cells coupled to a spare word line. Each spare row may be used to functionally replace a defective row in the same CAM block or in any other CAM block by programming the address of the defective row into the corresponding spare address decoder.

Abstract: The supply voltage to which a delay circuit's buffer stages are coupled is adjusted in response to changes in temperature according to a predetermined relationship to maintain a substantially constant buffer stage gate delay over temperature variations. Decreasing gate delays resulting from decreases in temperature are offset by decreasing the supply voltage, which in turn increases gate delays. Conversely, increasing gate delays resulting from increases in temperature are offset by increasing the supply voltage, which in turn decreases gate delays. In some embodiments, a control circuit is connected to the reference voltage circuit that supplies VCC to the delay circuit, and adjusts VCC in response to temperature to maintain substantially constant gate delay over temperature. In one embodiment, the control circuit includes a microprocessor and a look-up table containing desired supply voltage versus temperature mappings.