Abstract: A method for dividing the frequency of a signal using a configurable dividing ratio is disclosed. An input signal with a first frequency is received at clocked switches in a frequency divider with a configurable dividing ratio. Non-clocked switches inside the frequency divider are operated to select one of multiple dividing ratios. An output signal is output with a second frequency that is the first frequency divided by the selected dividing ratio.

Abstract: A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).

Abstract: Scheduling real-time Quality of Service (QoS) data flows in a large-scale wireless communications system uses credit allocation to active QoS flows based on quality-of-service weights, and the credits are measured in dimensionless units of air interface slot capacity. Scheduling addresses inactive QoS flows with no data pending for transmission that may accumulate up to a burst credits limit based upon a fair share of all credits that would be allocated in a 100% busy system. Intermittent flows such as echo requests or keyboard input can thereby get immediate service by using their burst credits. The flow with the highest credit accumulation is serviced first and may use up to a full time slot (or system quanta) of air interface time reducing header encapsulation overhead when payload sizes (and spectral efficiency) are low. Additive and multiplicative aspects age the negative credits back to zero whenever a flow overspends its credit allocation.

Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

Abstract: Providing for remote field testing of mobile communication devices is described herein. By way of example, network initiated data received at a mobile device or like device activated on a mobile network can be monitored. Further, an over the air (OTA) message sent by the mobile network to the monitored device can be identified and forwarded to a test device. Additionally, an IP gateway of the mobile network can be monitored for mobile originated pull messages or network originated push messages associated with or identifying the test device. A data translator can reconfigure or reroute data to and from the mobile device and mobile network utilizing information associated with the activated device. Accordingly, remote data exchange can be implemented even if the mobile device is not pre-activated on the mobile network.

Abstract: The disclosed embodiments provide for methods and systems for flexibly allocating a shared frequency spectrum to a plurality of users, the spectrum may have a first number of segments, each segment having a second number of clusters associated with a certain sector/cell. In one aspect, a method for flexibly allocating a shared frequency spectrum to a plurality of users comprises the acts of fixedly assigning a first group of clusters to a first group of users, such that the first group of users stay fixed to the assigned clusters, and assigning a second group of clusters to a second group of users, such that the second group of users hop within the assigned clusters.

Abstract: A circuit for a voltage controlled oscillator (VCO) buffer is described. The circuit includes a first capacitor connected to an input of the VCO buffer that is connected to a VCO core. The circuit also includes a second capacitor connected to the input of the VCO buffer and the gate of a p-type metal-oxide-semiconductor field effect (PMOS) transistor. The circuit further includes a first switch connected to the first capacitor and the gate of the PMOS transistor. The circuit also includes a third capacitor connected to the input of the VCO buffer. The circuit further includes a fourth capacitor connected to the input of the VCO buffer and the gate of an n-type metal-oxide-semiconductor field effect (NMOS) transistor. The circuit also includes a second switch connected to the third capacitor and the gate of the NMOS transistor.

Abstract: System(s) and method(s) are provided for dynamically scaling switching frequencies and clock sources of switched mode power supplies (SMPSs) in a mobile station. Switching frequency is scaled to an optimal value in response to at least one of (i) a change in mode of operation for wireless communication employed by the mobile station, an additional mode of operation is triggered, (ii) a change in operation conditions of a set of loads associated with functionality of the mobile is determined, or (iii) an LO spur set-off by a SMPS in the presence of an interference signal with a frequency splitting from an operational band that matches the SMPS frequency or at least one of its harmonics. Switching frequencies can be selected from a lookup table, or through an analysis of switching frequencies available to the mobile and operational criteria. A set of clock sources can provide an ensemble of switching frequencies.

Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.

Abstract: A method for measuring non-linear characteristics of a power amplifier is described. A calibration waveform is calculated during a testing procedure period. Amplitude characteristics of the calibration waveform at the output of the power amplifier are measured during the testing procedure period. Phase characteristics of the calibration waveform at the output of the power amplifier are measured during the testing procedure period. Pre-distortion techniques are configured based on the amplitude characteristics and the phase characteristics to be used during a normal operation period of a transmitter.

Abstract: Methods and apparatus for self testing a multiband voltage controlled oscillator (VCO) are disclosed. A tuning voltage of the VCO is adjusted where the output of the VCO does not affect the input to the VCO. Frequency bands in the VCO are selected. Output frequencies of the VCO are measured.

Abstract: An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.

Abstract: An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

Abstract: A multiple analog signal converter (100) simultaneously converts multiple analog signals (104,106) to digital signals (112, 114) using a single analog to digital converter (ADC) 102. A first analog signal (104) at a first center frequency and a second analog signal (106) at a second center frequency are processed by the ADC (102) to generate a composite digital signal (110) comprising a first digital signal (112) corresponding to the first analog signal (104) and a second digital signal (114) corresponding to the second analog signal (106). The composite digital signal (110) is digitally frequency shifted to recover the second digital signal (106). The first digital signal (104) is recovered by digitally filtering the composite digital signal (110). In some circumstances, a first radio frequency (RF) signal (118) and a second RF signal (122) are frequency shifted to generate the first analog signal (104) and second analog signal (106).

Abstract: A method for detecting the presence of a transmission signal in a wireless spectrum channel. The frequency of a signal is converted from a first frequency to a second frequency. The signal with the second frequency is filtered to remove signals that are not within the band of the second frequency. An averaged periodogram of the signal is calculated. A value of the averaged periodogram is compared to a threshold. The presence of the transmission signal is detected, if the value of the averaged periodogram exceeds the threshold.

Abstract: A probe card test interface is described. The probe card test interface includes a first frame configured to support a probe card circuit card assembly (CCA). The probe card CCA is configured to contact a semiconductor wafer with one or more test probes. The first frame is also configured to support a first group of electrical contact points, the first group of electrical contact point being electrically coupled to circuitry of the probe card CCA. A second frame is coupled to a test interface CCA, where the test interface CCA includes a second group of electrical contact points. A number of actuation devices are slidably mounted on the second frame. The actuation devices have a tip member configured to engage a lip of the first frame when the corresponding actuation device is moved to an engagement position.

Abstract: Techniques are disclosed for compensating for second-order distortion in a wireless communication device. In a zero-intermediate frequency (IF) or low-IF architecture, IM2 distortion generated by the mixer (20) results in undesirable distortion levels in the baseband output signal. A compensation circuit (104) provides a measure of the IM2 distortion current independent of the radio frequency (RF) pathway to generate an IM2 calibration current. The IM2 calibration current is combined with the baseband output signal to thereby eliminate the IM2 currents generated within the RF pathway. In one embodiment, the calibration is provided at the factory during final testing. In alternative embodiment, additional circuitry (156, 158) may be added to the wireless communication device to provide a pathway between the transmitter (150) and the receiver (146). The transmitter signal is provided to the receiver to permit automatic calibration of the unit.

Abstract: Various socket configurations having coaxial alignment and attachments are disclosed. The various socket configurations can use two-mount and three-mount configurations to facilitate adaptability to high density routing.

Abstract: Embodiments of the present invention are directed to switched-mode power supply (SMPS) circuits and methods thereof. The SMPS circuit receives information related to a future load change. For example, the information may be received at a decoder (e.g., a serial bus interface (SBI) decoder) from a microprocessor or microcontroller, such as a mobile station modem (MSM). The SMPS circuit may include an analog-to-digital converter configured to sample an output voltage of the SMPS circuit to determine a time when the future load change occurs. The SMPS circuit may further include a transient recovery circuit (TRC) for stabilizing the output voltage based on the received information when the future load change occurs. For example, the TRC calculates a duty cycle used to transition states of switches of the SMPS circuit to compensate for the future load change.

Abstract: A method and an apparatus powers down an analog integrated circuit. A power down circuit is electrically coupled to the analog circuit and is adapted to power down the analog circuit in response to receiving a power down signal. A node protection circuit is electrically coupled to the analog circuit and is adapted to provide a predetermined voltage potential to at least one predetermined node in the analog circuit in response to receiving the power down signal when a voltage potential at the at least one predetermined node is not determined by the power down circuit.