Abstract: A memory device output buffer circuit provides an output data signal only when data is valid. According to the present invention, the circuit for a memory read function provides a pair of signals equilibrated prior to each read operation. Data is valid when the signals are complementary. For a tristate output, the complementary condition enables the output buffer. In a semiconductor dynamic random access memory (DRAM) connectable to a bidirectional data bus, the three-state output buffer of the present invention is not enabled during a read operation until data is valid. Spurious output data signals are prevented from consuming power. As an additional benefit, the bus is not dedicated to the memory when valid data is not yet available.

Abstract: Serial clock cycle time for a serial read operation in a semiconductor memory is reduced by partitioning the read operation into a sensing operation, a counter operation and an output operation, and conducting all three operations simultaneously in a pipelined fashion. To carry out the new method, the memory effectively is pipelined by providing a read register (92) between the sensing flip-flop (90) and the output latch/driver (96), and by isolating the address counter (48) from the address decoder circuitry (56) by inserting an isolation buffer (52). Additionally, the serial access time is reduced by conducting a look-ahead load (72) of a first tap address at the conclusion of a read transfer cycle, without waiting for the serial clock signal (SC) to begin the read cycle.

Abstract: A device for holding and covering a gas pilot used to ignite a gas burner includes a rigid bracket for holding the pilot and a rigid cover over the pilot. The bracket includes a bifurcated plate that grips the pilot and holds it in fixed relation to the gas burner. The cover extends over the pilot to protect it from being misaligned by heavy objects and from being extinguished by drafts and by materials heated over the burner. The device increases the reliability of the gas burner.

Abstract: A method for fabricating a high value, vertically integrated resistor begins with an integrated circuit having an unpassivated upper surface that includes designated circuit nodes to be placed in series with the vertical resistor. A layer of passivating material such as boro-phospho silicate glass is deposited on the upper surface of the integrated circuit. Polysilicon vias are formed that extend through the passivating layer and form an electrical ohmic contact with each designated circuit node. The polysilicon vias are subsequently ion implanted with oxygen or nitrogen to increase the resistance thereof to the final desired resistance, which can be greater than 100 megohms, and as much as a gigohm or a terohm. Finally, the vertical resistor is contacted with a metal layer formed on the surface of the passivating layer.