Abstract: A tank is set up to hold a precise volume of acid by first adjusting an overflow pipe to establish a volume that is larger than the desired volume and then adjusting the vertical position of a volume occupying element that extends above and below the surface of the acid. The apparatus includes a drain pipe for directing the acid to a tank that holds deionized water that the acid is mixed with. The bath is used for etching a silicon dioxide layer on a semiconductor wafer.

Abstract: A new method for detecting blind holes in the contact layer of a multi-chip semiconductor test wafer makes use of the fact that if the hole is not a blind hole, a subsequent etch step extends the hole a predetermined distance into the layer immediately underlying the contact layer. After a predetermined number of holes have been etched through the contact layer and for a predetermined distance into the layer underlying the contact layer, the contact layer is stripped to expose the holes in the underlying layer. These holes are scanned optically by a commercial apparatus that ordinarily detects wafer defects that resemble the holes. The missing holes are detected by comparing the holes of different chips on the test wafer. The test is particularly useful with a high density plasma etch because these holes typically have a very small diameter in relation to the thickness of the contact layer.

Abstract: A tool for placing an identifying mark on a semiconductor wafer has a bundle of optical fibers that can be illuminated in a pattern representing an identifying character. Light from the fibers is focused on a photoresist layer during wafer manufacture and a pattern of dots is etched into the wafer to represent the character. The dots are too small to be seen with the human eye but the character can be read by a human or by a machine. The character is etched as part of a conventional etch step in manufacturing the wafer and it is easily repeated as a series of manufacturing steps obscure the original mark.

Abstract: An open drain driver circuit and a Vss to Vdd FET with a merged layout structure are formed to provide a short path for an ESD current from an associated pad and either Vss or Vdd. The short path reduces the IR drop in the path and thereby maintains a lower voltage at the pad during an ESD event. The driver and the Vss to Vdd FET are each formed of one or more cells that each comprise two source diffusions, two gates, and a common drain diffusion. A frame of the opposite conductivity type as the drain and source diffusions surrounds the components of each cell. The driver and Vss to Vdd FET cells are formed closely adjacent and share common parts of the frame. Several configurations with merged layout structures are disclosed that provide a short ESD current path.

Abstract: A tank is set up to hold a precise volume of acid by first adjusting an overflow pipe to establish a volume that is larger than the desired volume and then adjusting the vertical position of a volume occupying element that extends above and below the surface of the acid. The apparatus includes a drain pipe for directing the acid to a tank that holds deionized water that the acid is mixed with. The bath is used for etching a silicon dioxide layer on a semiconductor wafer.

Abstract: In an improved method for etching a groove n the uppermost layer of a semiconductor wafer, a conventional anisotropic etch is performed to achieve a narrow groove and an isotropic etch is performed to widen the groove at the device surface and thereby round the edges where the walls of the groove meet the surface of the wafer. During a later step of applying a protective tape to the device side of the wafer to protect it during a step of grinding the back of the wafer, the rounded edges of the groove are unlikely to cut through the adhesive layer of the tape and thereby cause particles of adhesive to remain on the wafer surface when the tape is removes.

Abstract: An improved input buffer circuit of the type having a chain of FET inverter circuits has an FET connected in a feedback loop that functions like a Schmidt trigger and counteracts a hysteresis effect that causes variations in the delay of the inverter circuits and compensation for process variation. An FET is connected to conduct in its source-drain circuit between one of the power supply terminals and the interconnection node of two of the inverters in the chain. The gate of FET is connected to receive a signal from the output of one of the inverters. The hysteresis effect is characterized by different rising and falling paths at one knee of the transfer curve that describes the switching operation. The channel type of the FET and the polarity of the power supply terminal are selected to provide feedback during the transition where the knee occurs.

Abstract: An improved shield for preventing the contamination of a wafer back from resist is combined with process steps that further prevent this contamination. The shield is located where vortex like air currents could otherwise deposit the resist vapor on the wafer back. The shield has the general shape of a cylinder that is open at the top and closed at the bottom. The bottom provides an attachment to a conventional part of the wafer coater and also forms part of the shield. The sides are arranged to extend close to the wafer back at a radius just less than the radius of the wafer. In the improved process, the spindle of the wafer chuck is not rotated at more than 1200 revolutions per minute in any of the wafer spinning operations, and the conventional step of washing the wafer back with a solvent is performed only at the end of the other operations.

Abstract: A method for non-destructively testing for the concentration of a component of a film that is used for doping a region of a semiconductor wafer uses an image histogram of the light reflected from an array of points on the film and the underlying substrate. The image histogram has peaks that are characteristic of the composition of the film. Tests are run to establish the image histogram peaks for a film with a normal concentration of the components and for films with low and high concentrations. When the same test is made for the film of a production wafer, the concentration of the component is readily classified as normal, high, or low.

Abstract: An open drain FET driver circuit at an input-output pad of a semiconductor chip and a frame of the same conductivity type as the drain and source diffusions of the driver is formed around the driver (or partly around the driver). The frame is connected to Vdd and forms the diffusion for the Vdd end of a field FET. The drain of the driver forms the diffusion for the pad end of this field FET and the pad to Vdd FET breaks down in response to an ESD voltage between the pad and Vdd and provides a path for ESD current that the open drain driver itself does not provide. Optionally, a second field FET is formed between the source of the driver FET and the frame and this FET conducts an ESD current between the pad and Vdd in series with the driver. With this cell array structure, the junction capacitance which the ESD protection devices contribute to the pad can be significantly reduced for high speed I/O applications.

Abstract: An improved method for sectioning a semiconductor wafer using a focused ion beam (FIB) apparatus permits a clearer image of the site of the cut to be formed from secondary electrons produced by the beam. The clearer image helps the operator of the FIB apparatus to make a more accurate cut. Before the FIB cut is made, a laser is used to cut into the wafer to expose the lowermost layer of silicon dioxide. This oxide and any oxide splatters from the laser cut are then removed with an oxide etcher. The FIB cut can then be made without splattering silicon dioxide over the area being viewed. A low beam current is used for the FIB cut.

Abstract: A test sample with a film and an underlying substrate representing part of a semiconductor wafer is prepared for a stud pull test by a process that includes maintaining the sample in boiling salt water for a few hours. When an epoxy stud is attached to the film of the sample and the clamped assembly is baked for a about an hour, the stud is firmly attached to the film and in an otherwise conventional pull test, the film breaks loose from the substrate (or the stud breaks from the epoxy) before the stud breaks from the film.

Abstract: A system for pumping resist to a wafer coating machine includes a line that returns a selected proportion of the resist entering the resist pump to the resist supply tank. The return line to the tank is connected to the pump outlet at a higher point than the pump outlet to the wafer coating machine, and the resist that is returned to the tank carries substantially all of the bubbles that are carried in the resist entering the tank. The bubbles are removed from the resist in the tank and the resist can be used normally.

Abstract: A gauge marker system has a flexible track that fits around the circumference of a gauge housing and carries one or more markers that extend over the face of the gauge to indicate a dial position that is to be noticed by a person using the gauge. The markers can be slid along the track to a selected position. The track is adapted to be fastened to the gauge by a cable tie that lies in a groove on the track.

Abstract: An improved method for grinding a semiconductor chip to prepare it for scanning with SEM to view a defect includes the step of forming an electrically conductive coating on the top surface of the chip. The coating is made under a mask that produces a U shaped conductive pattern so that an electrical path is formed on the top surface of the chip between two corners of the pattern. An initial resistance measurement is made for this path and a known amount of the chip below the U shape is ground away and a second resistance measurement is made. From these measurements, a calculation is made that gives the resistance when the chip has been ground to a selected section line. The grinding operation then proceeds until this resistance is reached, and the usual practice of visually checking the chip during the grinding operation is avoided. The mask creates a point at the bottom of the U shape that points to the defect.