Abstract: A method executed by a computer under the control of a program includes the establishing of a compound structure in the form of a virtual unit of multi-dimensional storage. The compound structure includes a rack with a horizontal arrangement of target structures linked by an alias backbone representing a dimension of information. The horizontal arrangement of target structures selectively includes further compound structures and base structures containing data, in any combination. The compound structure is referenced to obtain information. The method is particularly useful in On-Line Analytical Processing (OLAP).

Abstract: A method and apparatus improve the thermal interface between a heat sink and a semiconductor. A support member is attached to a bias plate to facilitate a fixed connection with a surface. The bias plate has a beam for alignment with a heat sink that is attached to the semiconductor. The bias plate is attached to the support member such that the support member forces the beam against the heat sink to improve the thermal interface between the heat sink and the semiconductor. In the method, a heat sink is attached to a semiconductor, and a pivoting beam is biased against the heat sink such that the thermal interface with the semiconductor is improved.

Abstract: A method of repairing a substrate includes the step of excavating a well in the substrate with an electrical discharge machining operation. A wire is then delivered to the well. Simultaneously, laser energy is routed to the well such that the laser energy intersects with the wire to produce a reconstruction weld in the well. A tool delivery system with an electrical discharge machining tool head and a reconstruction welding tool head is used to perform the excavation and welding operations.

Abstract: A probe includes an elongated body with a top surface, a bottom surface, a first side wall between the top surface and the bottom surface, and a second side wall between the top surface and the bottom surface. An end is defined by the bottom surface converging into a tip, an isotropically etched portion of the first side wall converging into the tip, and an isotropically etched portion of the second side wall converging into the tip. The elongated body is less than approximately 700 &mgr;m wide and less than approximately 200 &mgr;m thick. The elongated body may incorporate a fluid channel. The elongated body may be formed of silicon that is not doped with Boron. In such a configuration, integrated circuitry or a micromachined device, such as a heater or pump may also be formed on the device. A number of novel processing techniques are associate with the fabrication of the device. The device may be formed by relying solely on isotropic etching.

Abstract: A method of monitoring event queue operations includes the step of responding to a set of run-time messages resulting from an operation performed with a graphical user interface. The set of messages is routed to a customized event queue module for processing. The customized event queue module reports operations associated with the set of messages. This information can be used for debugging, tracing, and event recording. The customized event queue module operates without altering the operation of the event queue. Thus, the invention can be used without altering proprietary software defining the operation of the event queue.

Abstract: A method of partitioning logic into a programmable logic device includes the steps of synthesizing a logic design into a network of hierarchical components. Each hierarchical component is then mapped to a minimum number of logic array blocks in a programmable logic device. The mapping operation may be performed by independently synthesizing the hierarchical components into a network of virtual logic elements, assigning the virtual logic elements to virtual logic array blocks, and mapping the virtual logic array blocks to the logic array blocks in the programmable logic device.

Abstract: A circuit for processing source code with associated array bounds limitations includes an execution unit that generates a register value signal and an index number signal corresponding to an array value defined in a source code instruction. A primary register is connected to the execution unit. The primary register produces a base memory address signal in response to the register value signal. A shadow register is also connected to the execution unit. The shadow register produces an array bound value signal in response to the register value signal. An address computation circuit is connected to the execution unit and the primary register. The address computation circuit generates an effective memory address signal based upon the base memory address signal and the index number signal. An address comparison circuit generates an array bound error signal when an effective memory address associated with the effective memory address signal exceeds an array bound value associated with the array bound value signal.

Abstract: A laser communication system includes a first laser to generate a laser signal with femtosecond pulses. A first grating spectrally disperses the femtosecond pulses of the laser signal. A modulator converts the femtosecond pulses of the laser signal into coded words. A second grating spectrally recombines the coded words of the laser signal. A first telescope launches the laser signal. A second telescope receives the laser signal. A second laser generates a set of reference pulses. A non-linear crystal combines the set of reference pulses and the laser signal so as to create an output signal only when the laser signal and the reference pulses temporally coincide. A detector records the output.

Abstract: A random access memory cell includes a forward inverter and a feedback inverter connected to the forward inverter. The feedback inverter includes a ground access transistor configured to selectively connect and isolate the feedback inverter to ground. The ground access transistor is isolated from ground in response to a first digital state global clear signal generated during a global clear state. A set of random access memory cells are simultaneously programmed to store identical values in response to the first digital state global clear signal during the global clear state. The ground access transistor is connected to ground in response to a second digital state global clear signal generated during a programming state. Selected random access memory cells are programmed to store selected values in response to the second digital state global clear signal during the programming state.

Abstract: A heat spreading apparatus includes a first planar body for attachment to a heat generating surface which results in a hot region and a cool region on the first planar body. A second planar body connected to the first planar body is used to define a void between the first planar body and the second planar body. The void includes a planar capillary path and a non-capillary region. A fluid positioned within the void distributes heat by vaporizing the fluid from the planar capillary path in the hot region, condensing the fluid in the non-capillary region in the cool region, and moving from the non-capillary region to the planar capillary path in the hot region through capillarity.