Patents Represented by Attorney, Agent or Law Firm Winstead Sechrest & Minick
  • Patent number: 7100039
    Abstract: A mechanism to acquire and deploy (“bootstrap”) software files, particularly testcase files, across multiple hosts and platforms is provided. A software package is created and a predetermined bootstrap executable file is built into the package. A process on each host on which the software files are to be deployed extracts the bootstrap file and executes it. Each bootstrap executable builds corresponding software files into the software package. The process then extracts the files corresponding to its particular process from the software package.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventor: Jeffrey O. Fisher
  • Patent number: 7097820
    Abstract: This invention relates generally to carbon fiber produced from single-wall carbon nanotube (SWNT) molecular arrays. In one embodiment, the carbon fiber which comprises an aggregation of substantially parallel carbon nanotubes comprises more than one molecular array. Another embodiment of this invention is a large cable-like structure with enhanced tensile properties comprising a number of smaller separate arrays. In another embodiment, a composite structure is disclosed in which a central core array of metallic SWNTs is surrounded by a series of smaller circular non-metallic SWNT arrays.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: August 29, 2006
    Assignee: William Marsh Rice University
    Inventors: Daniel T. Colbert, Hongjie Dai, Jason H. Hafner, Andrew G. Rinzler, Richard E. Smalley
  • Patent number: 7100035
    Abstract: When activities are operated in parallel, and there is only one status display, an ordered list is implemented with three methods of access: insertion at the top, removal from anywhere, and read of the top item. Items kept on this list are the status codes or words for the activities that are currently in progress. When a new activity begins, its status code or word is inserted at the top of the list. Whenever an activity completes, its code or word is removed from the list regardless of its location in the list, and in such a way as to preserve the order of the remaining entries in the list. Whenever the top entry in the list changes (whether through an insertion or removal), the single status display is updated to show the new top value.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: August 29, 2006
    Assignee: International Business Machines Corporation
    Inventors: James Joseph Babka, Chris Alan Schwendiman
  • Patent number: 7093479
    Abstract: The invention concerns a method and apparatus for indicating a parameter of a transmitted fluid. One embodiment of the invention comprises a fluid source operatively coupled to a conduit for transmitting a fluid from the fluid source. In addition, a sensor detects a parameter of the fluid, such as the percent oxygen content of the fluid. In response to the sensor detecting the parameter of the fluid, an indicator illuminates a portion of the conduit if a predetermined condition, such as a minimum percent oxygen content of the fluid, is satisfied.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: August 22, 2006
    Assignee: International Business Machines Corporation
    Inventors: Viktors Berstis, Michael P. Carlson, Yen-Fu Chen, John W. Dunsmoir, Randolph M. Forlenza, John P. Kaemmerer, Francis X. Kinstler, Sheryl S. Kinstler
  • Patent number: 7092985
    Abstract: A method for managing workloads and associated distributed processing system are disclosed that identify the capabilities of distributed devices connected together through a wide variety of communication systems and networks and utilize those capabilities to organize, manage and distribute project workloads to the distributed devices.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: August 15, 2006
    Assignee: United Devices, Inc.
    Inventor: Edward A. Hubbard
  • Patent number: 7093106
    Abstract: A single rename register array is used in an SMT processor. Two bits are added to each register address of the rename register array, one for bit for thread zero (CTB0) and one bit for thread one (CTB1). The CTB bits are all set to a logic value on power on or start-up. A control instruction (CI) that sets control bits used by other instructions is assigned a register in the rename register array having an address designated as pointer (PTR) address. When a control instruction with an assigned entry with PTR address M completes, then the CTB bit at the PTR address M is flipped to its opposite logic state; likewise, its Valid bit is set to a “not” Valid state. The self resetting CTB bit is used to determine whether an issued instruction sources a register in the rename register array or a corresponding architected register.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Asit S. Ambekar, Dung Q. Nguyen, Raymond C. Yeung
  • Patent number: 7090819
    Abstract: The present invention relates to an all gas-phase process for the purification of single-wall carbon nanotubes and the purified single-wall carbon nanotube material. Known methods of single-wall carbon nanotube production result in a single-wall carbon nanotube product that contains single-wall carbon nanotubes in addition to impurities including residual metal catalyst particles and amounts of small amorphous carbon sheets that surround the catalyst particles and appear on the sides of the single-wall carbon nanotubes and “ropes” of single-wall carbon nanotubes. The purification process removes the extraneous carbon as well as metal-containing residual catalyst particles. The process comprises oxidation of the single-wall carbon nanotube material, reduction and reaction of a halogen-containing gas with the metal-containing species. The oxidation step may be done dry or in the presence of water vapor.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: August 15, 2006
    Assignee: William Marsh Rice University
    Inventors: Richard E. Smalley, Robert H. Hauge, Wan-Ting Chiang, Yuemei Yang, Kenneth A. Smith, Wilber Carter Kittrell, Zhenning Gu
  • Patent number: 7093073
    Abstract: A mechanism for caching Web services requests and responses, including testing an incoming request against the cached requests and associated responses is provided. The requests are selectively tested against the cached data in accordance with a set of policies. If a request selected hits in the cache, the response is served up from the cache. Otherwise, the request is passed to the corresponding Web-services server/application. Additionally, a set of predetermined cache specifications for generating request identifiers may be provided. The identifier specification may be autonomically adjusted by determining cache hit/cache miss ratios over the set of identifier specifications and over a set of sample requests. The set of specifications may then be sorted to reflect the performance of the respective cache specification algorithms for the current mix of requests.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventor: Gregory Louis Truty
  • Patent number: 7091319
    Abstract: The present invention relates to fusion molecules composed of human interleukin-3 (hIL-3) variant or mutant proteins (muteins) functionally joined to a second colony stimulating factor (CSF), cytokine, lymphokine, interleukin or IL-3 variant. These hIL-3 variants contain amino acid substitutions and may also have amino acid deletions at both the N- and C-termini. The invention also relates to pharmaceutical compositions containing the fusion molecules and methods for using them.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 15, 2006
    Inventors: S. Christopher Bauer, Mark Allen Abrams, Sarah Ruth Braford-Goldberg, Marie Helena Caparon, Alan Michael Easton, Barbara Kure Klein, John Patrick McKearn, Peter O. Olins, Kumnan Paik, John Warren Thomas
  • Patent number: 7092142
    Abstract: A circuit for implementing a registration-free, contiguous conductive plane. A circuit may include a plurality of conductive structures in a first plane. The circuit may further include a contiguous conductive equipotential surface in a second plane parallel to the first plane. The circuit may further include activation means configured to adjust an electric field between the first and second planes thereby activating one or more structures in the first plane by increasing a potential difference between the first and second planes to a threshold level deemed to constitute an active state. The circuit may further include deactivation means configured to adjust the electric field between the first and second planes thereby deactivating one or more structures in the first plane by decreasing the potential difference between the first and second planes below a threshold level deemed to constitute a deactivated state.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: August 15, 2006
    Assignee: Uni-Pixel Displays, Inc.
    Inventors: Martin G. Selebrede, Lynn Essman
  • Patent number: 7093209
    Abstract: An system IC is partitioned into test ICs that have a sub-set of the functionality of the system IC. The test ICs have chip I/O pads conforming to a sub-set arrangement of the system IC chip I/O pads. A packaging module is designed to accept means for attaching and fanning-out the system IC chip I/O pads to lower density packaging I/O pads. A test IC is electrically coupled to the packaging module and tested by programming signals and power to the signal and power pads on the module packaging I/O pads corresponding to chip I/O pads for the test IC. Functionality of the system IC may be partitioned into a plurality of test ICs, each with chip I/O pads that conform to an individual sub-set of the system IC I/Os. Two or more of the plurality of test ICs are coupled to the system IC packaging module for testing.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: August 15, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mehrdad Mahanpour
  • Patent number: 7093111
    Abstract: A method and system for recovering a global history vector. In the event of a non-branch flush, a tag may be received by a queue configured to store information about branch instructions. The queue may read a copy of the global history vector from an entry indexed by the tag. This copy may be inserted in a global history vector mechanism (“GHV mechanism”) configured to manage the global history vector. If the flush operation is a flush to a group of instructions that contains no branch instructions and the tag does not equal the next-to-write pointer in the queue, then the queue may transmit a command to the GHV mechanism to enter a mode where the GHV mechanism does not update the global history vector until the next branch instruction is fetched.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Scott B. Frommer, Balaram Sinharoy
  • Patent number: 7089391
    Abstract: A system and method for managing a functional unit in a system using a data movement engine. An exemplary system may comprise a CPU coupled to a memory controller. The memory controller may include or couple to a data movement engine (DME). The memory controller may in turn couple to a system memory or other device which includes at least one functional unit. The DME may operate to transfer data to/from the system memory and/or the functional unit, as described herein. In one embodiment, the DME may also include multiple DME channels or multiple DME contexts. The DME may operate to direct the functional unit to perform operations on data in the system memory. For example, the DME may read source data from the system memory, the DME may then write the source data to the functional unit, the functional unit may operate on the data to produce modified data, the DME may then read the modified data from the functional unit, and the DME may then write the modified data to a destination in the system memory.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: August 8, 2006
    Assignee: Quickshift, Inc.
    Inventors: Peter D. Geiger, Manuel J. Alvarez, II, Thomas A. Dye
  • Patent number: 7082474
    Abstract: The present invention provides a method for providing data sharing and filed distribution in a distributed processing system. The distributed processing system identifies and utilizes the capabilities of distributed devices connected together through a wide variety of communication systems and networks and utilizes those capabilities to organize, manage and distribute project workloads to the distributed devices.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: July 25, 2006
    Assignee: United Devices, Inc.
    Inventor: Edward A. Hubbard
  • Patent number: 7080165
    Abstract: At system power on, a query is sent from a PCI or host-based controller to an attached codec for the vendor specific identification code associated with that codec. The PCI/host controller then sets its PCI vendor and subvendor ID's to match the specific system comprised of the controller and codec devices. That vendor specific identification code is then utilized within the PCI enumeration process to search for the specific modem driver associated with that codec.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: July 18, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Charles R. Boswell, Timothy C. Maleck, Brian Barnes
  • Patent number: 7080241
    Abstract: An apparatus and method for self-initiated instruction issuing are implemented. In a central processing unit (CPU) having a pipelined architecture, instructions are queued for issuing to the execution unit which will execute them. Instructions are issued each cycle, and an instruction should be selectable for issuing as soon as its source operands are available. An instruction in the issue queue having source operands depending on other, target, instructions to determine their value are signaled to the target instruction by a link mask in the queue entry corresponding to the target instruction. A bit in the link mask identifies the queue entry corresponding to the dependent instruction. When the target instruction issues to the execution unit, a bit is set in a predetermined portion of the queue entry containing the dependent instruction. The portion of the queue entry is associated with the source operand depending on the issuing instruction.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hung Qui Le, Hoichi Cheong
  • Patent number: 7074310
    Abstract: The invention relates to a process for sorting and separating a mixture of (n, m) type single-wall carbon nanotubes according to (n, m) type. A mixture of (n, m) type single-wall carbon nanotubes is suspended such that the single-wall carbon nanotubes are individually dispersed. The nanotube suspension can be done in a surfactant-water solution and the surfactant surrounding the nanotubes keeps the nanotube isolated and from aggregating with other nanotubes. The nanotube suspension is acidified to protonate a fraction of the nanotubes. An electric field is applied and the protonated nanotubes migrate in the electric fields at different rates dependent on their (n, m) type. Fractions of nanotubes are collected at different fractionation times. The process of protonation, applying an electric field, and fractionation is repeated at increasingly higher pH to separated the (n, m) nanotube mixture into individual (n, m) nanotube fractions.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: July 11, 2006
    Assignee: William Marsh Rice University
    Inventors: Richard E. Smalley, Robert H. Hauge, W. Carter Kittrell, Ramesh Sivarajan, Michael S. Strano, Sergei M. Bachilo, R. Bruce Weisman
  • Patent number: 7075797
    Abstract: A substantially rigid card having a first side and an opposing second side, a first connector end adapted to mate with a first expansion connector on a circuit board and a second connector end adapted to mate with a second expansion connector on the board. A first peripheral card connector is connected to the first side and electrically connected to the first connector end, wherein the first connector is of a first form factor and adapted to mate with a first peripheral card. A second peripheral card connector is connected to the second side and electrically connected to the second connector end, wherein the second connector is of a second form factor different from the first form factor and matable with a second peripheral card.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: July 11, 2006
    Assignee: Lenovo (Singapore) Pte Ltd.
    Inventors: Brian Hargrove Leonard, Michael Thano Matthews, Susan Sommers Moffatt, John David Swansey
  • Patent number: 7072351
    Abstract: Aspects for collision recovery interface support in a home phoneline networking alliance (HPNA) control chip are described. The aspects include providing transmit data path logic to receive and transmit data packets within the HPNA control chip. The transmit data path logic is consolidated to include a transmit state machine that handles interfacing the transmit data path logic to at least two separate collision recovery logic means of the HPNA control chip through a minimal number of generic interface signals.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peter K. Chow, Jenny L. Fischer
  • Patent number: D526220
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: August 8, 2006
    Assignee: Authentix, Inc.
    Inventors: Chester Wildey, Amber Ansari, Patrick Kindell, Jeremy Horvath, Jim Rittenburg, Paul Cronin