Patents Assigned to 2PAI SEMICONDUCTOR CO., LIMITED
  • Publication number: 20220224315
    Abstract: A latch circuit includes a first differential input terminal for receiving a first differential input signal and a second differential input terminal for receiving a second differential input signal. The circuit also includes a first switch comprising a first switch input terminal coupled to the first differential input terminal and a first output terminal, and a second switch comprising a second switch input terminal coupled to the second differential input terminal and a second output terminal. The circuit also includes a first cascade switch coupled to the first output terminal and a second cascade switch coupled to the second output terminal. The first differential input signal is characterized by a swing voltage of less than 300 mV and includes a first pulse component and a first non-zero voltage component, the first non-zero voltage component being attributed at least to the first switch and the first input resistor.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Applicant: 2Pai Semiconductor Co., Limited
    Inventor: Zhiwei Dong
  • Publication number: 20210359650
    Abstract: A digital isolator device which includes a first input buffer configured to receive a first differential signal from a transmitter and to provide a second differential signal, the first differential signal being characterized by a first magnitude, the second differential signal being characterized by a second magnitude, the first magnitude being greater than the second magnitude. The device also includes a second input buffer configured to receive a third differential signal from the transmitter and to provide a fourth differential signal, the second input buffer being coupled to the second ground terminal. The device also includes a common-mode circuit coupled to the second differential signal and the fourth differential signal, the common-mode circuit being configured to reduce a common-mode transient voltage, the common-mode transient voltage being associated with a voltage differential between the first ground terminal and the second ground terminal.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 18, 2021
    Applicant: 2Pai Semiconductor Co., Limited
    Inventor: Zhiwei DONG
  • Publication number: 20210021241
    Abstract: An isolation circuit and a method for providing isolation between two dies are provided. The isolation circuit includes: an isolation module, configured to generate an isolation signal based on an input signal from a first die and to provide isolation between the first die and a second die, where the isolation signal is smaller than the input signal in amplitude, and the first die is coupled with the second die; a latch module, configured to latch the isolation signal at a certain level and output a latched signal; an amplifier module, configured to amplify the latched signal. In the isolation circuit, a modulation module and a demodulation module can be saved.
    Type: Application
    Filed: September 18, 2020
    Publication date: January 21, 2021
    Applicant: 2Pai Semiconductor Co., Limited
    Inventor: Zhiwei DONG
  • Patent number: 10812027
    Abstract: An isolation circuit and a method for providing isolation between two dies are provided. The isolation circuit includes: an isolation module, configured to generate an isolation signal based on an input signal from a first die and to provide isolation between the first die and a second die, where the isolation signal is smaller than the input signal in amplitude, and the first die is coupled with the second die; a latch module, configured to latch the isolation signal at a certain level and output a latched signal; an amplifier module, configured to amplify the latched signal. In the isolation circuit, a modulation module and a demodulation module can be saved.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: October 20, 2020
    Assignee: 2PAI SEMICONDUCTOR CO., LIMITED
    Inventor: Zhiwei Dong
  • Publication number: 20190214974
    Abstract: A latch and an isolation circuit are provided. The latch includes a first-level substructure and at least one second-level substructure, the number of the at least one second-level substructure is k, and k is a positive integer greater than or equal to 1. The first-level substructure includes a first load having a first terminal coupled with a first port, a second load having a first terminal coupled with the first port, a first driving circuit having a control terminal coupled with a second terminal of the first load and a second terminal coupled with a second port, a second driving circuit having a control terminal coupled with a second terminal of the second load and a second terminal coupled with the second port. Each of the at least one second-level substructure includes a third load, a fourth load, a third driving circuit and a fourth driving circuit.
    Type: Application
    Filed: June 7, 2018
    Publication date: July 11, 2019
    Applicant: 2PAI SEMICONDUCTOR CO., LIMITED
    Inventor: Zhiwei DONG
  • Publication number: 20180342989
    Abstract: An isolation circuit and a method for providing isolation between two dies are provided. The isolation circuit includes: an isolation module, configured to generate an isolation signal based on an input signal from a first die and to provide isolation between the first die and a second die, where the isolation signal is smaller than the input signal in amplitude, and the first die is coupled with the second die; a latch module, configured to latch the isolation signal at a certain level and output a latched signal; an amplifier module, configured to amplify the latched signal. In the isolation circuit, a modulation module and a demodulation module can be saved.
    Type: Application
    Filed: May 25, 2018
    Publication date: November 29, 2018
    Applicant: 2PAI SEMICONDUCTOR CO., LIMITED
    Inventor: Zhiwei DONG