Abstract: A router with a routing layer that supports single or multiple routing protocols. The routing layer has at least two routing protocol computing entities, namely a first and a second routing protocol computing entities. Each routing protocol computing entity includes a CPU, a data storage medium in communication with the CPU and a program data stored in the data storage medium for execution by said CPU. The program data in each routing protocol computing entity implements different or the same routing protocols. This routing layer architecture is highly scalable.

Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells. Each cell communicates with at least one other cell of the array, thereby permitting an exchange of data packets to take place between the cells of the array. Each cell includes a memory for receiving a data packet from another cell of the array as well as a control entity to control release of a data packet toward a selected destination cell of the array at least in part on a basis of a degree of occupancy of the memory in the destination cell. In this way, scheduling is distributed amongst the cells of the switch fabric.

Abstract: The invention provides a chassis, a scalable router that includes a plurality of chassis and a method of upgrading a router. Each chassis includes a plurality of processing modules and a programmable interconnection module. Data connections are provided between each processing module on each chassis and the interconnection module on that chassis, and a data connection is provided between the interconnection module on each chassis and the interconnection module on at least one other chassis. In this way, the inter-chassis and intra-chassis connections pass through the programmable interconnection module, which may be used for concentrating the location of resources, such as opto-electronic and electro-optical converters, in a single card or unit. Moreover, the programmable nature of the switch fabric in each interconnection module is amenable to reconfiguration so as to support a change in that chassis' interconnection pattern that may be required for expanding the router's capacity.

Abstract: An adapter for use in the process of inspecting the end face of an optical fiber. The adapter is used as an interface between an inspection probe and a connector. The connector holds an the optical fiber end which has a surface. The adaptor comprises a positioning mechanism having an attachment portion for releasable attachment to the connector; and a fixture adapted for releasable attachment to the probe. The fixture is mounted to the positioning mechanism and is moveable relative to the attachment portion. The positioning mechanism permits movement of the probe for inspection of the surface.

Abstract: A method and system for regulating packet flow to a downstream entity capable of forwarding packets to a plurality of intermediate destinations. The method includes maintaining a database of queues, each queue in the database being associated with packets intended to be forwarded to a corresponding one of a plurality of final destinations via a corresponding one of the intermediate destinations. Each queue in the database is further associated with a state that is either active or inactive. Upon receipt of a message from the downstream entity indicating a reduced (increased) ability of a particular one of the intermediate destinations to accept packets intended to be forwarded to a particular one of the final destinations, the method provides for rendering inactive (active) the state of the queue associated with packets intended to be forwarded to the particular final destination via the particular intermediate destination.

Abstract: A router includes a routing layer and a switching layer. The routing layer includes a plurality of I/O ports for exchanging data with components external to the router. The switching layer is adapted to switch data packets between I/O ports of the routing layer. The switching layer includes an array of cells in communication with the routing layer for permitting exchange of data packets between the array of cells and the routing layer. Each cell includes a memory for receiving a data packet from the routing layer. The routing layer includes a controller to control release of a data packet toward a cell of the array at least in part on a basis of a degree of occupancy of the memory in the cell.

Abstract: Method, apparatus and software for processing sets of routing information in a router having a plurality of memory units accessible via separate access paths. The sets of routing information are typically routes received from neighbour nodes. The method includes creating a plurality of non-identical routing information subsets from each received set of routing information, accessing the memory units via the separate access paths and storing the routing information subsets created from a common set of routing information in respective ones of the plurality of memory units, By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.

Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of the array selected on a basis of the determined destination. Each cell further includes a plurality of receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets to the I/O interface.

Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell communicates with at least one other cell of the array, permitting an exchange of data packets between the cells of the array and an exchange of control information between the cells of the array. Each cell is operative to control transmission of data packets to other cells of the array at least in part on a basis of the control information. The control information is thus used to regulate the flow of data packets between cells.