Patents Assigned to 4D-S, Ltd.
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Patent number: 10833262Abstract: A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode; a first barrier layer, configured to substantially prevent the conduction of ions therethrough, where the first barrier layer is between the top electrode and the top contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m; and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, where the second barrier layer is between the memory layer and the bottom contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m.Type: GrantFiled: March 16, 2018Date of Patent: November 10, 2020Assignee: 4D-S, LTD.Inventors: Seshubabu Desu, Michael Van Buskirk
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Patent number: 10734576Abstract: A memory device is disclosed. The memory device includes a bottom contact. The memory device also includes a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure, where a first contact formed at an interface between the bottom contact and the memory layer is ohmic, and where a second contact formed at an interface between the memory layer and the top electrode is ohmic.Type: GrantFiled: March 16, 2018Date of Patent: August 4, 2020Assignee: 4D-S, LTD.Inventor: Seshubabu Desu
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Patent number: 10381558Abstract: A memory device is disclosed. The memory device includes a bottom electrode. The memory device also includes a memory layer connected to the bottom electrode, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a retention layer between the memory layer and the top electrode, where the retention layer has a variable ionic conductivity, where the retention layer is configured to selectively resist ionic conduction, and where the resistivity of the retention layer is less than 1×10-4 ohm-m.Type: GrantFiled: March 16, 2018Date of Patent: August 13, 2019Assignee: 4D-S, LTD.Inventors: Seshubabu Desu, Michael Van Buskirk
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Patent number: 10319907Abstract: A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.Type: GrantFiled: March 16, 2018Date of Patent: June 11, 2019Assignee: 4D-S, Ltd.Inventor: Seshubabu Desu
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Patent number: 9711714Abstract: Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-XCaXMnO3 (PCMO) layer, in an electrically biased sputtering chamber, above the insulator and the metal portions, to form one or more self-aligned RRAM cells above the first metal electrode; and depositing a second metal electrode layer above the PCMO layer.Type: GrantFiled: February 5, 2013Date of Patent: July 18, 2017Assignee: 4D-S LTD.Inventor: Makoto Nagashima
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Patent number: 9634247Abstract: A resistive memory device is disclosed. The memory device comprises one or more metal oxide layers. An oxygen vacancy or ion concentrations of the one or more metal oxide layer is controlled in the formation and the operation of the memory device to provide robust memory operation.Type: GrantFiled: March 15, 2013Date of Patent: April 25, 2017Assignee: 4D-S LTD.Inventors: Dongmin Chen, Lee Cleveland, Seshubabu Desu, Kurt Pfluger, Jean Yang-Scharlotta
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Patent number: 9058876Abstract: A resistive random access memory integrated circuit for use as a mass storage media and adapted for bulk erase by substantially simultaneously switching all memory cells to one of at least two possible resistive states. Bulk switching is accomplished by biasing all bottom electrodes within an erase area to a voltage lower than that of the top electrodes, wherein the erase area can comprise the entire memory array of the integrated circuit or else a partial array. Alternatively the erase area may be a single row and, upon receiving the erase command, the row address is advanced automatically and the erase step is repeated until the entire array has been erased.Type: GrantFiled: June 21, 2013Date of Patent: June 16, 2015Assignee: 4D-S, LTDInventors: Lee Cleveland, Franz Michael Schuette
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Publication number: 20140376299Abstract: A resistive random access memory integrated circuit for use as a mass storage media and adapted for bulk erase by substantially simultaneously switching all memory cells to one of at least two possible resistive states. Bulk switching is accomplished by biasing all bottom electrodes within an erase area to a voltage lower than that of the top electrodes, wherein the erase area can comprise the entire memory array of the integrated circuit or else a partial array. Alternatively the erase area may be a single row and, upon receiving the erase command, the row address is advanced automatically and the erase step is repeated until the entire array has been erased.Type: ApplicationFiled: June 21, 2013Publication date: December 25, 2014Applicant: 4D-S, LTD.Inventors: Lee Cleveland, Franz Michael Schuette
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Patent number: 8709891Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.Type: GrantFiled: June 14, 2013Date of Patent: April 29, 2014Assignee: 4D-S Ltd.Inventors: Zhida Lan, Dongmin Chen
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Publication number: 20130279236Abstract: Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.Type: ApplicationFiled: June 14, 2013Publication date: October 24, 2013Applicant: 4D-S, LTD.Inventors: Zhida Lan, Dongmin Chen
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Publication number: 20130233701Abstract: A plasma source includes a hexagonal hollow cathode, the cathode including six targets and six magnets to generate and maintain a high density plasma; and an anode located beneath the cathode. A second hexagonal hollow cathode can be positioned concentric to the hexagonal hollow cahode.Type: ApplicationFiled: April 22, 2013Publication date: September 12, 2013Applicant: 4D-S, LTDInventor: Makoto Nagashima
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Patent number: 8466032Abstract: Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr1-XCaXMnO3 (PCMO) layer above the insulator and the metal portions, wherein X is between approximately 0.3 and approximately 0.5, to form one or more self-aligned RRAM cells above the first metal electrode; and depositing a second metal electrode layer above the PCMO layer.Type: GrantFiled: December 27, 2012Date of Patent: June 18, 2013Assignee: 4D-S, Ltd.Inventor: Makoto Nagashima