Abstract: A real-time scheduler for scheduling periodic access to a shared resource by a number of channels. The channel period for each channel is represented by a channel value partitioned into an extra-fine value, a fine value, and a coarse value. The fine value is in units of access intervals, the length of time of each access. The coarse value is in units of scheduling periods, the maximum number of access intervals that can be represented by the fine value. The extra-fine value is in units of a number that evenly divides the access interval. During each scheduling period all non-zero coarse values are decremented by one and then if zero, indicate that the next cell send time for that channel falls in the next scheduling period. Concurrently, a fine process executes repeatedly in which all fine values that had a zero coarse value at the end of the previous scheduling period are compared to find the smallest value.

Abstract: An asynchronous pipeline that is divided into separate data and signal chains by moving the data register load signal buffer outside of the closed loop that generates the output request event from the input request event, causing the output request event to occur before output data is available. Matched delays between adjacent pipeline stages permit data and signals to move from stage to stage without problem. Matched delays between stages are possible if: (1) every stage has the same loading; (2) logically adjacent stages are physically located next to each other; (3) the buffered data register load signal has enough drive to latch data reliably; and (4) the delay from input request event to output request event is greater than the latch time of the data register. Input and output circuits transform the internal signals of the pipeline to the correct asynchronous signals for asynchronous source and destination devices or to the correct synchronous signals for synchronous source and destination devices.