Abstract: The present invention relates in general to the field of generation of precise electrical signals, in particular, to a technique for providing accurate delays of signals using a controllable delay line, and is applicable to the areas of high speed communication and memory testing equipment. According to the present invention, an auxiliary reference channel having a delay line which is identical to the main delay line is incorporated into vernier silicon die to allow automatic adjustment of the delay in the main delay line using a reference periodical signal applied to the auxiliary delay line.

Abstract: An electrical connector for establishing an interconnection between the contact pads of a printed circuit board device under test (DUT) and an electrical device. The connector includes a flexible circuit carrying the interconnect between the DUT and pcb, which is moved into position by the inflation of a bladder that changes its form to press the contacts on the flexible circuit onto the contact positions of the DUT. The bladder is constrained to minimize its expansion. The flexible circuit is not constrained except at the point it is mated with the circuit board of the equipment driving the DUT. The path of the flexible circuit is shaped by fixed formers and terminates at the bladder. This avoids impinging on the DUT area outwith the contact zone. The connector includes variants which have a lock to secure the DUT in place and sensors to determine when the DUT is fully inserted.

Abstract: A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality.

Abstract: The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips. A data transmission means for high-speed transmission of digital data is proposed, the data transmission means comprising: at least one driver for driving a transmission line; and a timing deskewing means connected thereto, wherein the timing deskewing means comprises a storage means for recording and storing information on skew caused by inter-symbol interference and cross-talk influence in the transmission line, for at least one data pattern transmitted through the transmission line; and an adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate for the above skew.

Abstract: Automatic test equipment for memory device testing provides continuous high-speed testing by intelligent pausing a timer when a buffer memory is full or nearly full, the timer being paused is capable of properly maintaining refresh and clock functions for semiconductor devices.

Abstract: A system for transformation of memory device addresses between different memory device topologies, each topology having its address space, providing the use of minimum memory space and time required for storage and computing defect data and also the flexibility of approach which allows mapping of memory device divided into an arbitrary number of tiles, each tile having different mapping scheme from a wide spectrum of mapping classes.

Abstract: A system, a method and a computer program product for defining transforms of cell addresses between different memory device topologies providing the use of minimum memory space and time required for storage and computing defect data and also the flexibility of approach offering a user friendly interface and simplification of the transformation procedure.

Abstract: A system for reducing or obviating the requirement for a large amount of defect capture memory in memory test and analysis systems by compressing test results. The compression means system reduces or replaces the fault capture memory in the test system or workstation or both, a major cost in test system, while providing for subsequent regeneration of the test results, either without loss, or with the loss of certain features immaterial to the application.