Patents Assigned to Adaptec, Inc.
  • Publication number: 20120210058
    Abstract: Methods, systems, and computer programs for managing storage using a solid state drive (SSD) read cache memory are presented. One method includes an operation for determining whether data corresponding to a read request is available in a SSD memory when the read request causes a miss in a memory cache. The read request is served from the SSD memory when the data is available in the SSD memory, and when the data is not available in the SSD memory, SSD memory tracking logic is invoked and the read request is served from a hard disk drive. Invoking the SSD memory tracking logic includes determining whether a fetch criteria for the data has been met, and loading the data corresponding to the read request in the SSD memory when the fetch criteria has been met. The use of the SSD as a read cache improves memory performance for random data reads.
    Type: Application
    Filed: April 24, 2012
    Publication date: August 16, 2012
    Applicant: Adaptec, Inc.
    Inventors: Steffen Mittendorff, Dieter Massa
  • Patent number: 7895464
    Abstract: A RAID system includes a pair of RAID controllers adapted to operate in active-active mode, each controller including a cache memory and at least one SAS/SATA I/O chip connected to a plurality of hard disk drives. Each SAS/SATA I/O chip includes more SAS/SATA ports than required to carry data to the hard drives. The caches in the respective controllers are synchronized via the extra SAS/SATA ports in each controller.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: February 22, 2011
    Assignee: Adaptec, Inc.
    Inventor: William E. Lynn
  • Patent number: 7783035
    Abstract: A network node is disclosed. The network node includes a host processor. The network node also includes an integrated circuit. The integrated circuit includes a hardware portion configured to perform a first set of TCP acceleration tasks that require a first speed level. The integrated circuit also includes a network protocol processor configured to perform a second set of TCP acceleration tasks that require a second speed level, which is lower than the first speed level. The integrated circuit further includes an embedded processor configured to perform a third set of TCP acceleration tasks that require a third speed level, which is lower than the second speed level. The network node further includes a plurality of data paths configured to couple the integrated circuit to the host processor, the plurality of data paths being implemented based on different protocols.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: August 24, 2010
    Assignee: Adaptec, Inc.
    Inventors: Todd Sperry, Sivakumar Munnangi, Shridhar Mukund
  • Publication number: 20100211731
    Abstract: Methods, systems, and computer programs for managing storage in a computer system using a solid state drive (SSD) read cache memory are presented. The method includes receiving a read request, which causes a miss in a cache memory. After the cache miss, the method determines whether the data to satisfy the read request is available in the SSD memory. If the data is in SSD memory, the read request is served from the SSD memory. Otherwise, SSD memory tracking logic is invoked and the read request is served from a hard disk drive (HDD). Additionally, the SSD memory tracking logic monitors access requests to pages in memory, and if a predefined criteria is met for a certain page in memory, then the page is loaded in the SSD. The use of the SSD as a read cache improves memory performance for random data reads.
    Type: Application
    Filed: February 19, 2009
    Publication date: August 19, 2010
    Applicant: Adaptec, Inc.
    Inventors: Steffen Mittendorff, Dieter Massa
  • Patent number: 7770147
    Abstract: A method for generating hardware description language source files is provided. The method includes extracting an input/output (I/O) list and building a port list declaration file from the I/O list. The method also includes building a default instantiation file according to renaming rules and interpreting coding constructs to determine both variable types and sizes. The method further includes generating a sensitivity list.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: August 3, 2010
    Assignee: Adaptec, Inc.
    Inventors: Marc Spitzer, John Packer
  • Patent number: 7765502
    Abstract: A method for generating hardware description language source files is provided. The method includes extracting an input/output (I/O) list and building a port list declaration file from the I/O list. The method also includes building a default instantiation file according to renaming rules and interpreting coding constructs to determine both variable types and sizes. The method further includes generating a sensitivity list.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: July 27, 2010
    Assignee: Adaptec, Inc.
    Inventors: Marc Spitzer, John Packer
  • Patent number: 7743308
    Abstract: A method and system for generating parity symbols and rebuilding data symbols in a RAID system. The method includes receiving a command to generate a desired parity or data symbol using an XOR relationship between some of a plurality of parity and data symbols. A symbol of the plurality of parity and data symbols is input to an XOR accumulator, the symbol being included in the XOR relationship. Additional symbols of the plurality of parity and data symbols are input to the XOR accumulator. Each time that an additional symbol is input and is included in the XOR relationship, an XOR operation is performed between the symbol in the XOR accumulator and the additional symbol, thus obtaining a resulting symbol that replaces the previous symbol in the XOR accumulator. After every symbol included in the XOR relationship has undergone an XOR operation, the symbol in the XOR accumulator is output as the desired parity or data symbol.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: June 22, 2010
    Assignee: Adaptec, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 7711793
    Abstract: A method for storing data is provided which includes transmitting a storage operation request to one of at least two controllers where the at least two controllers is capable of managing communication with a plurality of targets. The method further includes directing the storage operation request to an operational one of the at least two controllers when the one of the at least two controllers is inoperable. The method also includes processing the storage operation request with the operational one of the at least two controllers.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 4, 2010
    Assignee: Adaptec, Inc.
    Inventor: Andrew W. Wilson
  • Patent number: 7702948
    Abstract: A computer-implemented method of automatically configuring a platform of storage devices includes querying components of the platform to gather information about the capability of the platform, locating one or more storage devices within the platform, automatically determining one or more RAID levels that are supported by the platform, and automatically configuring one or more storage devices within the platform as a RAID system having a particular RAID level, where the particular RAID level is selected based on the capability of the platform.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: April 20, 2010
    Assignee: Adaptec, Inc.
    Inventors: Dean Kalman, Clinton D. Knight
  • Patent number: 7698625
    Abstract: A dual parity hardware architecture that enables data to be read from each sector only once and performs both the P parity and Q parity from the single data source. The Q parity calculator provides parallel processing capabilities so that multiple parity operations are performed on the same sector simultaneously. The dual parity hardware architecture provides flexibility in restoring data, generating parity, and updating parity for differing data sector sizes.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: April 13, 2010
    Assignee: Adaptec, Inc.
    Inventor: Robert L. Horn
  • Patent number: 7672742
    Abstract: A method for reducing audio latency when executing program instructions for processing audio data is provided. In this method, a top threshold value and a bottom threshold value are provided. A determination is then made as to the amount of audio data stored in an audio buffer of an audio renderer. Thereafter, the amount is compared with the top threshold value and the bottom threshold value, and accordingly, an audio data feed to the audio renderer is adjusted incrementally such that the amount is between the top threshold value and the bottom threshold value.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: March 2, 2010
    Assignee: Adaptec, Inc.
    Inventors: Buay Hock Ng, Jianyun Zhou, ShunNian Zhai
  • Patent number: 7600132
    Abstract: Various embodiments are provided for authenticating an embedded device on a motherboard. An exemplary embodiment includes generating a unique authentication code (UAC) based on a serial number for a motherboard, and providing the UAC to a computer system having the motherboard. A determination is then made as to whether the provided UAC is correct for the motherboard, and an option ROM BIOS designed for the embedded device is executed when the provided UAC is correct for the motherboard.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: October 6, 2009
    Assignee: Adaptec, Inc.
    Inventor: Fadi A. Mahmoud
  • Patent number: 7577742
    Abstract: A method and apparatus for account creation without administrator interaction on a computer network is provided. Specifically, a continuously operating program on a file server creates accounts without the intervention of a system administrator. The continuously operating program on the file server monitors connection points on the file server for requests to create an account. Upon receiving a request from a client computer to create an account, the continuously operating program on the file server processes the request by authenticating a requestor on the client computer and an account identifier transmitted by the requester. After resolving the account identifier, the continuously operating program creates the account in a directory structure and configures software settings for accessing the account. Subsequently, the program notifies the requestor of the newly created account.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: August 18, 2009
    Assignee: Adaptec, Inc.
    Inventor: Thomas Roy Prohofsky
  • Patent number: 7571258
    Abstract: A method for efficiently processing layers of a data packet is provided. The method initiates with defining a pipeline of processors communicating with a distributed network and CPU of a host system. Then, a data packet from the distributed network is received into a first stage of the pipeline. Next, the data packet is processed to remove a header associated with the first stage. Then, the processed data packet is transmitted to a second stage. The operations of processing and transmitting the processed data packet are repeated for successive stages until a header associated with a final stage has been removed. Then, the data packet is transmitted to the CPU of the host system. It should be appreciated that the header is not necessarily transformed at each stage. For example, suitable processing that does not strip the header may be applied at each stage.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: August 4, 2009
    Assignee: Adaptec, Inc.
    Inventors: Shridhar Mukund, Anjan Mitra, Mahesh Gopalan
  • Patent number: 7565521
    Abstract: A method for managing use of a fixed memory space of a computer system is provided. The computer system interfaces with controllers for managing operation of devices that operate with the computer system. The method includes determining whether sufficient memory is allocated in the fixed memory space for initializing code for the controllers, and jumping to swappable portion of the fixed memory space. The method also includes executing code in the swappable portion of the fixed memory space. The method further includes loading additional code needed to initialize the controllers from an external memory chip to the fixed memory space where the additional code is executed to complete initialization of the controllers of the computer system.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: July 21, 2009
    Assignee: Adaptec, Inc.
    Inventor: Fadi A. Mahmoud
  • Patent number: 7555701
    Abstract: A method of calculating parity for an m-storage element failure in a networked array of storage elements. A first set of n XOR relationships is derived, each first set relationship containing n data symbols from n storage elements and one parity symbol from a first set of parity symbols. A second set of n XOR relationships is derived, each second set relationship containing at least n?1 data symbols from at least n?1 storage elements and one parity symbol from a second set of parity symbols. Additional sets of relationships are derived such that a total of m sets of relationships are derived. Each of the additional sets of relationships are composed of up to (n+i?1)Ci?1 relationships, where i indicates the numbered set of relationship. Using the first, second and additional sets of derived relationships, scripts are generated to resolve unresolved symbols resulting from possible m-storage element failure combinations.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: June 30, 2009
    Assignee: Adaptec, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 7549020
    Abstract: A method for protecting memory is provided. The method includes reading a block of data from a storage drive and writing the block of data to a first memory portion and a second memory portion. The method also includes managing the first memory portion and the second memory portion to protect the block of data. The block of data can be recovered from a non-failing portion in case either the first memory portion or the second memory portion fails.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: June 16, 2009
    Assignee: Adaptec, Inc.
    Inventor: Fadi Mahmoud
  • Patent number: 7523257
    Abstract: A method of managing bad blocks in a RAID storage system. The system restores physical storage media and stripe redundancy by reassigning sectors and creating a bad block tracking structure. The bad block tracking structure consists of a volume map, a redundancy group table, and a bad block table that stores a bad block list. Redundancy is achieved through RAID 1 or RAID 10 mirroring rather than through the parity restoration required by conventional systems. The tracking structure returns media error status data to the originating host on volume read commands. The structure accepts volume write data from the originating host and then deletes the bad block tracking structure.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: April 21, 2009
    Assignee: Adaptec, Inc.
    Inventors: Robert L. Horn, Virgil V. Wilkins
  • Patent number: 7509473
    Abstract: A system for mapping between logical addresses and storage units of a plurality of storage volumes which comprise a storage system. For each volume, logical addresses are mapped to storage units using a volume mapping table. Each volume mapping table is comprised of a plurality of segments. Each segment need not be contiguously allocated to another segment of the same table. Thus, each volume mapping table can be independently expanded or reduced without affecting other volume mapping tables. A hash function, a hash table, a segment table, and a redundancy group descriptor table may also be used to help manage the segments of the volume mapping tables.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: March 24, 2009
    Assignee: Adaptec, Inc.
    Inventors: Robert L. Horn, Virgil V. Wilkins
  • Patent number: RE41397
    Abstract: Disclosed is a process for driving a network interface card. The process includes monitoring the status of a plurality of ports connected between a computer and a network. Detecting a failure in one of the plurality of ports connected to the network. Re-assigning data transmitted over the failed one of the plurality of ports to an active port of the plurality of ports selected in a round robin technique . The process further including receiving data over one of the plurality of ports designated as a primary receiving port. Preferably, when the failed one of the plurality of ports is the primary receiving port, the receiving tasks are assigned to a next active port selected in a round robin technique .
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: June 22, 2010
    Assignee: Adaptec, Inc.
    Inventors: Faisal Latif, Pramod Sharma, Suleman Saya, Jim J. Kuhfeld